git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv7/socfpga/misc.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <miiphy.h>
  10 #include <netdev.h>
  11 #include <asm/arch/reset_manager.h>
  12 #include <asm/arch/system_manager.h>
  13 #include <asm/arch/dwmmc.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 static struct socfpga_system_manager *sysmgr_regs =
  18         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  19
  20 int dram_init(void)
  21 {
  22         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  23         return 0;
  24 }
  25
  26 /*
  27  * DesignWare Ethernet initialization
  28  */
  29 #ifdef CONFIG_DESIGNWARE_ETH
  30 int cpu_eth_init(bd_t *bis)
  31 {
  32 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
  33         const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
  34 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
  35         const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
  36 #else
  37 #error "Incorrect CONFIG_EMAC_BASE value!"
  38 #endif
  39
  40         /* Initialize EMAC. This needs to be done at least once per boot. */
  41
  42         /*
  43          * Putting the EMAC controller to reset when configuring the PHY
  44          * interface select at System Manager
  45          */
  46         socfpga_emac_reset(1);
  47
  48         /* Clearing emac0 PHY interface select to 0 */
  49         clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
  50                      SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
  51
  52         /* configure to PHY interface select choosed */
  53         setbits_le32(&sysmgr_regs->emacgrp_ctrl,
  54                      SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
  55
  56         /* Release the EMAC controller from reset */
  57         socfpga_emac_reset(0);
  58
  59         /* initialize and register the emac */
  60         return designware_initialize(CONFIG_EMAC_BASE,
  61                                      CONFIG_PHY_INTERFACE_MODE);
  62 }
  63 #endif
  64
  65 #ifdef CONFIG_DWMMC
  66 /*
  67  * Initializes MMC controllers.
  68  * to override, implement board_mmc_init()
  69  */
  70 int cpu_mmc_init(bd_t *bis)
  71 {
  72         return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
  73                                   CONFIG_HPS_SDMMC_BUSWIDTH, 0);
  74 }
  75 #endif
  76
  77 #if defined(CONFIG_DISPLAY_CPUINFO)
  78 /*
  79  * Print CPU information
  80  */
  81 int print_cpuinfo(void)
  82 {
  83         puts("CPU   : Altera SOCFPGA Platform\n");
  84         return 0;
  85 }
  86 #endif
  87
  88 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
  89 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
  90 int overwrite_console(void)
  91 {
  92         return 0;
  93 }
  94 #endif
  95
  96 int arch_cpu_init(void)
  97 {
  98         /*
  99          * If the HW watchdog is NOT enabled, make sure it is not running,
 100          * for example because it was enabled in the preloader. This might
 101          * trigger a watchdog-triggered reboot of Linux kernel later.
 102          */
 103 #ifndef CONFIG_HW_WATCHDOG
 104         socfpga_watchdog_reset();
 105 #endif
 106         return 0;
 107 }
 108
 109 int misc_init_r(void)
 110 {
 111         return 0;
 112 }