2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm-offsets.h>
38 ldr pc, _undefined_instruction
39 ldr pc, _software_interrupt
40 ldr pc, _prefetch_abort
45 #ifdef CONFIG_SPL_BUILD
46 _undefined_instruction: .word _undefined_instruction
47 _software_interrupt: .word _software_interrupt
48 _prefetch_abort: .word _prefetch_abort
49 _data_abort: .word _data_abort
50 _not_used: .word _not_used
53 _pad: .word 0x12345678 /* now 16*4=64 */
55 _undefined_instruction: .word undefined_instruction
56 _software_interrupt: .word software_interrupt
57 _prefetch_abort: .word prefetch_abort
58 _data_abort: .word data_abort
59 _not_used: .word not_used
62 _pad: .word 0x12345678 /* now 16*4=64 */
63 #endif /* CONFIG_SPL_BUILD */
68 .balignl 16,0xdeadbeef
69 /*************************************************************************
71 * Startup Code (reset vector)
73 * do important init only if we don't start from memory!
74 * setup Memory and board specific bits prior to relocation.
75 * relocate armboot to ram
78 *************************************************************************/
82 .word CONFIG_SYS_TEXT_BASE
86 * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s).
87 * U-Boot runs on the AVP first, setting things up for the CPU (PLLs,
88 * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU
89 * to pick up its reset vector, which points here.
97 * These are defined in the board-specific linker script.
101 .word __bss_start - _start
103 .global _image_copy_end_ofs
105 .word __image_copy_end - _start
109 .word __bss_end__ - _start
115 #ifdef CONFIG_USE_IRQ
116 /* IRQ stack memory (calculated at run-time) */
117 .globl IRQ_STACK_START
121 /* IRQ stack memory (calculated at run-time) */
122 .globl FIQ_STACK_START
127 /* IRQ stack memory (calculated at run-time) + 8 bytes */
128 .globl IRQ_STACK_START_IN
133 * the actual reset code
138 * set the cpu to SVC32 mode
145 #if defined(CONFIG_OMAP34XX)
146 /* Copy vectors to mask ROM indirect addr */
147 adr r0, _start @ r0 <- current position of code
148 add r0, r0, #4 @ skip reset vector
149 mov r2, #64 @ r2 <- size to copy
150 add r2, r0, r2 @ r2 <- source end address
151 mov r1, #SRAM_OFFSET0 @ build vect addr
152 mov r3, #SRAM_OFFSET1
154 mov r3, #SRAM_OFFSET2
157 ldmia r0!, {r3 - r10} @ copy from source address [r0]
158 stmia r1!, {r3 - r10} @ copy to target address [r1]
159 cmp r0, r2 @ until source end address [r2]
160 bne next @ loop until equal */
161 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
162 /* No need to copy/exec the clock code - DPLL adjust already done
163 * in NAND/oneNAND Boot.
165 bl cpy_clk_code @ put dpll adjust code behind vectors
166 #endif /* NAND Boot */
168 /* the mask ROM code should have PLL and others stable */
169 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
173 /* Set stackpointer in internal RAM to call board_init_f */
175 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
176 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
180 /*------------------------------------------------------------------------------*/
183 * void relocate_code (addr_sp, gd, addr_moni)
185 * This "function" does not return, instead it continues in RAM
186 * after relocating the monitor code.
191 mov r4, r0 /* save addr_sp */
192 mov r5, r1 /* save addr of gd */
193 mov r6, r2 /* save addr of destination */
195 /* Set up the stack */
201 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
202 beq clear_bss /* skip relocation */
203 mov r1, r6 /* r1 <- scratch for copy_loop */
204 ldr r3, _image_copy_end_ofs
205 add r2, r0, r3 /* r2 <- source end address */
208 ldmia r0!, {r9-r10} /* copy from source address [r0] */
209 stmia r1!, {r9-r10} /* copy to target address [r1] */
210 cmp r0, r2 /* until source end address [r2] */
213 #ifndef CONFIG_SPL_BUILD
215 * fix .rel.dyn relocations
217 ldr r0, _TEXT_BASE /* r0 <- Text base */
218 sub r9, r6, r0 /* r9 <- relocation offset */
219 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
220 add r10, r10, r0 /* r10 <- sym table in FLASH */
221 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
222 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
223 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
224 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
226 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
227 add r0, r0, r9 /* r0 <- location to fix up in RAM */
230 cmp r7, #23 /* relative fixup? */
232 cmp r7, #2 /* absolute fixup? */
234 /* ignore unknown type of fixup */
237 /* absolute fix: set location to (offset) symbol value */
238 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
239 add r1, r10, r1 /* r1 <- address of symbol in table */
240 ldr r1, [r1, #4] /* r1 <- symbol value */
241 add r1, r1, r9 /* r1 <- relocated sym addr */
244 /* relative fix: increase location by offset */
249 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
254 .word __rel_dyn_start - _start
256 .word __rel_dyn_end - _start
258 .word __dynsym_start - _start
260 #endif /* #ifndef CONFIG_SPL_BUILD */
263 #ifdef CONFIG_SPL_BUILD
264 /* No relocation for SPL */
268 ldr r0, _bss_start_ofs
270 mov r4, r6 /* reloc addr */
274 mov r2, #0x00000000 /* clear */
276 clbss_l:str r2, [r0] /* clear loop... */
282 * We are done. Do not return, instead branch to second part of board
283 * initialization, now running from RAM.
287 * If I-cache is enabled invalidate it
289 #ifndef CONFIG_SYS_ICACHE_OFF
290 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
291 mcr p15, 0, r0, c7, c10, 4 @ DSB
292 mcr p15, 0, r0, c7, c5, 4 @ ISB
294 ldr r0, _board_init_r_ofs
298 /* setup parameters for board_init_r */
299 mov r0, r5 /* gd_t */
300 mov r1, r6 /* dest_addr */
305 .word board_init_r - _start
308 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
309 /*************************************************************************
311 * CPU_init_critical registers
313 * setup important registers
314 * setup memory timing
316 *************************************************************************/
321 mov r0, #0 @ set up for MCR
322 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
323 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
324 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
325 mcr p15, 0, r0, c7, c10, 4 @ DSB
326 mcr p15, 0, r0, c7, c5, 4 @ ISB
329 * disable MMU stuff and caches
331 mrc p15, 0, r0, c1, c0, 0
332 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
333 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
334 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
335 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
336 #ifdef CONFIG_SYS_ICACHE_OFF
337 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
339 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
341 mcr p15, 0, r0, c1, c0, 0
344 * Jump to board specific initialization...
345 * The Mask ROM will have already initialized
346 * basic memory. Go here to bump up clock rate and handle
347 * wake up conditions.
349 mov ip, lr @ persevere link reg across call
350 bl lowlevel_init @ go setup pll,mux,memory
351 mov lr, ip @ restore link
352 mov pc, lr @ back to my caller
355 #ifndef CONFIG_SPL_BUILD
357 *************************************************************************
361 *************************************************************************
366 #define S_FRAME_SIZE 72
388 #define MODE_SVC 0x13
392 * use bad_save_user_regs for abort/prefetch/undef/swi ...
393 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
396 .macro bad_save_user_regs
397 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
399 stmia sp, {r0 - r12} @ Save user registers (now in
401 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
403 ldmia r2, {r2 - r3} @ get values for "aborted" pc
404 @ and cpsr (into parm regs)
405 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
409 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
410 mov r0, sp @ save current stack into r0
414 .macro irq_save_user_regs
415 sub sp, sp, #S_FRAME_SIZE
416 stmia sp, {r0 - r12} @ Calling r0-r12
417 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
418 @ a reserved stack spot would
420 stmdb r8, {sp, lr}^ @ Calling SP, LR
421 str lr, [r8, #0] @ Save calling PC
423 str r6, [r8, #4] @ Save CPSR
424 str r0, [r8, #8] @ Save OLD_R0
428 .macro irq_restore_user_regs
429 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
431 ldr lr, [sp, #S_PC] @ Get PC
432 add sp, sp, #S_FRAME_SIZE
433 subs pc, lr, #4 @ return & move spsr_svc into
438 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
441 str lr, [r13] @ save caller lr in position 0
443 mrs lr, spsr @ get the spsr
444 str lr, [r13, #4] @ save spsr in position 1 of
447 mov r13, #MODE_SVC @ prepare SVC-Mode
449 msr spsr, r13 @ switch modes, make sure
451 mov lr, pc @ capture return pc
452 movs pc, lr @ jump to next instruction &
456 .macro get_bad_stack_swi
457 sub r13, r13, #4 @ space on current stack for
459 str r0, [r13] @ save R0's value.
460 ldr r0, IRQ_STACK_START_IN @ get data regions start
461 @ spots for abort stack
462 str lr, [r0] @ save caller lr in position 0
464 mrs r0, spsr @ get the spsr
465 str lr, [r0, #4] @ save spsr in position 1 of
467 ldr r0, [r13] @ restore r0
468 add r13, r13, #4 @ pop stack entry
471 .macro get_irq_stack @ setup IRQ stack
472 ldr sp, IRQ_STACK_START
475 .macro get_fiq_stack @ setup FIQ stack
476 ldr sp, FIQ_STACK_START
483 undefined_instruction:
486 bl do_undefined_instruction
492 bl do_software_interrupt
512 #ifdef CONFIG_USE_IRQ
519 irq_restore_user_regs
524 /* someone ought to write a more effective fiq_save_user_regs */
527 irq_restore_user_regs
543 #endif /* CONFIG_USE_IRQ */
544 #endif /* CONFIG_SPL_BUILD */