2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm-offsets.h>
38 ldr pc, _undefined_instruction
39 ldr pc, _software_interrupt
40 ldr pc, _prefetch_abort
46 _undefined_instruction: .word undefined_instruction
47 _software_interrupt: .word software_interrupt
48 _prefetch_abort: .word prefetch_abort
49 _data_abort: .word data_abort
50 _not_used: .word not_used
53 _pad: .word 0x12345678 /* now 16*4=64 */
57 .balignl 16,0xdeadbeef
58 /*************************************************************************
60 * Startup Code (reset vector)
62 * do important init only if we don't start from memory!
63 * setup Memory and board specific bits prior to relocation.
64 * relocate armboot to ram
67 *************************************************************************/
71 .word CONFIG_SYS_TEXT_BASE
75 * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s).
76 * U-Boot runs on the AVP first, setting things up for the CPU (PLLs,
77 * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU
78 * to pick up its reset vector, which points here.
86 * These are defined in the board-specific linker script.
90 .word __bss_start - _start
94 .word __bss_end__ - _start
100 #ifdef CONFIG_USE_IRQ
101 /* IRQ stack memory (calculated at run-time) */
102 .globl IRQ_STACK_START
106 /* IRQ stack memory (calculated at run-time) */
107 .globl FIQ_STACK_START
112 /* IRQ stack memory (calculated at run-time) + 8 bytes */
113 .globl IRQ_STACK_START_IN
118 * the actual reset code
123 * set the cpu to SVC32 mode
130 #if defined(CONFIG_OMAP34XX)
131 /* Copy vectors to mask ROM indirect addr */
132 adr r0, _start @ r0 <- current position of code
133 add r0, r0, #4 @ skip reset vector
134 mov r2, #64 @ r2 <- size to copy
135 add r2, r0, r2 @ r2 <- source end address
136 mov r1, #SRAM_OFFSET0 @ build vect addr
137 mov r3, #SRAM_OFFSET1
139 mov r3, #SRAM_OFFSET2
142 ldmia r0!, {r3 - r10} @ copy from source address [r0]
143 stmia r1!, {r3 - r10} @ copy to target address [r1]
144 cmp r0, r2 @ until source end address [r2]
145 bne next @ loop until equal */
146 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
147 /* No need to copy/exec the clock code - DPLL adjust already done
148 * in NAND/oneNAND Boot.
150 bl cpy_clk_code @ put dpll adjust code behind vectors
151 #endif /* NAND Boot */
153 /* the mask ROM code should have PLL and others stable */
154 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
158 /* Set stackpointer in internal RAM to call board_init_f */
160 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
161 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
165 /*------------------------------------------------------------------------------*/
168 * void relocate_code (addr_sp, gd, addr_moni)
170 * This "function" does not return, instead it continues in RAM
171 * after relocating the monitor code.
176 mov r4, r0 /* save addr_sp */
177 mov r5, r1 /* save addr of gd */
178 mov r6, r2 /* save addr of destination */
180 /* Set up the stack */
185 #ifndef CONFIG_SPL_BUILD
187 beq clear_bss /* skip relocation */
189 mov r1, r6 /* r1 <- scratch for copy_loop */
190 ldr r3, _bss_start_ofs
191 add r2, r0, r3 /* r2 <- source end address */
194 ldmia r0!, {r9-r10} /* copy from source address [r0] */
195 stmia r1!, {r9-r10} /* copy to target address [r1] */
196 cmp r0, r2 /* until source end address [r2] */
199 #ifndef CONFIG_SPL_BUILD
201 * fix .rel.dyn relocations
203 ldr r0, _TEXT_BASE /* r0 <- Text base */
204 sub r9, r6, r0 /* r9 <- relocation offset */
205 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
206 add r10, r10, r0 /* r10 <- sym table in FLASH */
207 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
208 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
209 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
210 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
212 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
213 add r0, r0, r9 /* r0 <- location to fix up in RAM */
216 cmp r7, #23 /* relative fixup? */
218 cmp r7, #2 /* absolute fixup? */
220 /* ignore unknown type of fixup */
223 /* absolute fix: set location to (offset) symbol value */
224 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
225 add r1, r10, r1 /* r1 <- address of symbol in table */
226 ldr r1, [r1, #4] /* r1 <- symbol value */
227 add r1, r1, r9 /* r1 <- relocated sym addr */
230 /* relative fix: increase location by offset */
235 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
240 ldr r0, _bss_start_ofs
242 mov r4, r6 /* reloc addr */
245 mov r2, #0x00000000 /* clear */
247 clbss_l:str r2, [r0] /* clear loop... */
251 #endif /* #ifndef CONFIG_SPL_BUILD */
254 * We are done. Do not return, instead branch to second part of board
255 * initialization, now running from RAM.
259 * If I-cache is enabled invalidate it
261 #ifndef CONFIG_SYS_ICACHE_OFF
262 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
263 mcr p15, 0, r0, c7, c10, 4 @ DSB
264 mcr p15, 0, r0, c7, c5, 4 @ ISB
266 ldr r0, _board_init_r_ofs
270 /* setup parameters for board_init_r */
271 mov r0, r5 /* gd_t */
272 mov r1, r6 /* dest_addr */
277 .word board_init_r - _start
280 .word __rel_dyn_start - _start
282 .word __rel_dyn_end - _start
284 .word __dynsym_start - _start
286 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
287 /*************************************************************************
289 * CPU_init_critical registers
291 * setup important registers
292 * setup memory timing
294 *************************************************************************/
299 mov r0, #0 @ set up for MCR
300 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
301 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
302 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
303 mcr p15, 0, r0, c7, c10, 4 @ DSB
304 mcr p15, 0, r0, c7, c5, 4 @ ISB
307 * disable MMU stuff and caches
309 mrc p15, 0, r0, c1, c0, 0
310 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
311 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
312 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
313 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
314 #ifdef CONFIG_SYS_ICACHE_OFF
315 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
317 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
319 mcr p15, 0, r0, c1, c0, 0
322 * Jump to board specific initialization...
323 * The Mask ROM will have already initialized
324 * basic memory. Go here to bump up clock rate and handle
325 * wake up conditions.
327 mov ip, lr @ persevere link reg across call
328 bl lowlevel_init @ go setup pll,mux,memory
329 mov lr, ip @ restore link
330 mov pc, lr @ back to my caller
333 *************************************************************************
337 *************************************************************************
342 #define S_FRAME_SIZE 72
364 #define MODE_SVC 0x13
368 * use bad_save_user_regs for abort/prefetch/undef/swi ...
369 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
372 .macro bad_save_user_regs
373 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
375 stmia sp, {r0 - r12} @ Save user registers (now in
377 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
379 ldmia r2, {r2 - r3} @ get values for "aborted" pc
380 @ and cpsr (into parm regs)
381 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
385 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
386 mov r0, sp @ save current stack into r0
390 .macro irq_save_user_regs
391 sub sp, sp, #S_FRAME_SIZE
392 stmia sp, {r0 - r12} @ Calling r0-r12
393 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
394 @ a reserved stack spot would
396 stmdb r8, {sp, lr}^ @ Calling SP, LR
397 str lr, [r8, #0] @ Save calling PC
399 str r6, [r8, #4] @ Save CPSR
400 str r0, [r8, #8] @ Save OLD_R0
404 .macro irq_restore_user_regs
405 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
407 ldr lr, [sp, #S_PC] @ Get PC
408 add sp, sp, #S_FRAME_SIZE
409 subs pc, lr, #4 @ return & move spsr_svc into
414 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
417 str lr, [r13] @ save caller lr in position 0
419 mrs lr, spsr @ get the spsr
420 str lr, [r13, #4] @ save spsr in position 1 of
423 mov r13, #MODE_SVC @ prepare SVC-Mode
425 msr spsr, r13 @ switch modes, make sure
427 mov lr, pc @ capture return pc
428 movs pc, lr @ jump to next instruction &
432 .macro get_bad_stack_swi
433 sub r13, r13, #4 @ space on current stack for
435 str r0, [r13] @ save R0's value.
436 ldr r0, IRQ_STACK_START_IN @ get data regions start
437 @ spots for abort stack
438 str lr, [r0] @ save caller lr in position 0
440 mrs r0, spsr @ get the spsr
441 str lr, [r0, #4] @ save spsr in position 1 of
443 ldr r0, [r13] @ restore r0
444 add r13, r13, #4 @ pop stack entry
447 .macro get_irq_stack @ setup IRQ stack
448 ldr sp, IRQ_STACK_START
451 .macro get_fiq_stack @ setup FIQ stack
452 ldr sp, FIQ_STACK_START
459 undefined_instruction:
462 bl do_undefined_instruction
468 bl do_software_interrupt
488 #ifdef CONFIG_USE_IRQ
495 irq_restore_user_regs
500 /* someone ought to write a more effective fiq_save_user_regs */
503 irq_restore_user_regs