2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm-offsets.h>
35 #include <asm/system.h>
36 #include <linux/linkage.h>
40 ldr pc, _undefined_instruction
41 ldr pc, _software_interrupt
42 ldr pc, _prefetch_abort
47 #ifdef CONFIG_SPL_BUILD
48 _undefined_instruction: .word _undefined_instruction
49 _software_interrupt: .word _software_interrupt
50 _prefetch_abort: .word _prefetch_abort
51 _data_abort: .word _data_abort
52 _not_used: .word _not_used
55 _pad: .word 0x12345678 /* now 16*4=64 */
57 _undefined_instruction: .word undefined_instruction
58 _software_interrupt: .word software_interrupt
59 _prefetch_abort: .word prefetch_abort
60 _data_abort: .word data_abort
61 _not_used: .word not_used
64 _pad: .word 0x12345678 /* now 16*4=64 */
65 #endif /* CONFIG_SPL_BUILD */
70 .balignl 16,0xdeadbeef
71 /*************************************************************************
73 * Startup Code (reset vector)
75 * do important init only if we don't start from memory!
76 * setup Memory and board specific bits prior to relocation.
77 * relocate armboot to ram
80 *************************************************************************/
84 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
85 .word CONFIG_SPL_TEXT_BASE
87 .word CONFIG_SYS_TEXT_BASE
91 * These are defined in the board-specific linker script.
95 .word __bss_start - _start
97 .global _image_copy_end_ofs
99 .word __image_copy_end - _start
103 .word __bss_end - _start
109 #ifdef CONFIG_USE_IRQ
110 /* IRQ stack memory (calculated at run-time) */
111 .globl IRQ_STACK_START
115 /* IRQ stack memory (calculated at run-time) */
116 .globl FIQ_STACK_START
121 /* IRQ stack memory (calculated at run-time) + 8 bytes */
122 .globl IRQ_STACK_START_IN
127 * the actual reset code
133 * set the cpu to SVC32 mode
142 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
143 * Continue to use ROM code vector only in OMAP4 spl)
145 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
146 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
147 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
148 bic r0, #CR_V @ V = 0
149 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
151 /* Set vector address in CP15 VBAR register */
153 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
156 /* the mask ROM code should have PLL and others stable */
157 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
164 /*------------------------------------------------------------------------------*/
166 #ifndef CONFIG_SPL_BUILD
168 * void relocate_code (addr_sp, gd, addr_moni)
170 * This "function" does not return, instead it continues in RAM
171 * after relocating the monitor code.
175 mov r4, r0 /* save addr_sp */
176 mov r5, r1 /* save addr of gd */
177 mov r6, r2 /* save addr of destination */
181 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
182 beq relocate_done /* skip relocation */
183 mov r1, r6 /* r1 <- scratch for copy_loop */
184 ldr r3, _image_copy_end_ofs
185 add r2, r0, r3 /* r2 <- source end address */
188 ldmia r0!, {r9-r10} /* copy from source address [r0] */
189 stmia r1!, {r9-r10} /* copy to target address [r1] */
190 cmp r0, r2 /* until source end address [r2] */
194 * fix .rel.dyn relocations
196 ldr r0, _TEXT_BASE /* r0 <- Text base */
197 sub r9, r6, r0 /* r9 <- relocation offset */
198 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
199 add r10, r10, r0 /* r10 <- sym table in FLASH */
200 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
201 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
202 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
203 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
205 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
206 add r0, r0, r9 /* r0 <- location to fix up in RAM */
209 cmp r7, #23 /* relative fixup? */
211 cmp r7, #2 /* absolute fixup? */
213 /* ignore unknown type of fixup */
216 /* absolute fix: set location to (offset) symbol value */
217 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
218 add r1, r10, r1 /* r1 <- address of symbol in table */
219 ldr r1, [r1, #4] /* r1 <- symbol value */
220 add r1, r1, r9 /* r1 <- relocated sym addr */
223 /* relative fix: increase location by offset */
228 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
237 .word __rel_dyn_start - _start
239 .word __rel_dyn_end - _start
241 .word __dynsym_start - _start
242 ENDPROC(relocate_code)
246 ENTRY(c_runtime_cpu_setup)
248 * If I-cache is enabled invalidate it
250 #ifndef CONFIG_SYS_ICACHE_OFF
251 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
252 mcr p15, 0, r0, c7, c10, 4 @ DSB
253 mcr p15, 0, r0, c7, c5, 4 @ ISB
258 #if !defined(CONFIG_TEGRA)
259 /* Set vector address in CP15 VBAR register */
261 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
266 ENDPROC(c_runtime_cpu_setup)
268 /*************************************************************************
270 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
271 * __attribute__((weak));
273 * Stack pointer is not yet initialized at this moment
274 * Don't save anything to stack even if compiled with -O0
276 *************************************************************************/
277 ENTRY(save_boot_params)
278 bx lr @ back to my caller
279 ENDPROC(save_boot_params)
280 .weak save_boot_params
282 /*************************************************************************
286 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
287 * CONFIG_SYS_ICACHE_OFF is defined.
289 *************************************************************************/
294 mov r0, #0 @ set up for MCR
295 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
296 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
297 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
298 mcr p15, 0, r0, c7, c10, 4 @ DSB
299 mcr p15, 0, r0, c7, c5, 4 @ ISB
302 * disable MMU stuff and caches
304 mrc p15, 0, r0, c1, c0, 0
305 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
306 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
307 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
308 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
309 #ifdef CONFIG_SYS_ICACHE_OFF
310 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
312 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
314 mcr p15, 0, r0, c1, c0, 0
316 #ifdef CONFIG_ARM_ERRATA_716044
317 mrc p15, 0, r0, c1, c0, 0 @ read system control register
318 orr r0, r0, #1 << 11 @ set bit #11
319 mcr p15, 0, r0, c1, c0, 0 @ write system control register
322 #ifdef CONFIG_ARM_ERRATA_742230
323 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
324 orr r0, r0, #1 << 4 @ set bit #4
325 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
328 #ifdef CONFIG_ARM_ERRATA_743622
329 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
330 orr r0, r0, #1 << 6 @ set bit #6
331 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
334 #ifdef CONFIG_ARM_ERRATA_751472
335 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
336 orr r0, r0, #1 << 11 @ set bit #11
337 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
340 mov pc, lr @ back to my caller
341 ENDPROC(cpu_init_cp15)
343 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
344 /*************************************************************************
346 * CPU_init_critical registers
348 * setup important registers
349 * setup memory timing
351 *************************************************************************/
354 * Jump to board specific initialization...
355 * The Mask ROM will have already initialized
356 * basic memory. Go here to bump up clock rate and handle
357 * wake up conditions.
359 b lowlevel_init @ go setup pll,mux,memory
360 ENDPROC(cpu_init_crit)
363 #ifndef CONFIG_SPL_BUILD
365 *************************************************************************
369 *************************************************************************
374 #define S_FRAME_SIZE 72
396 #define MODE_SVC 0x13
400 * use bad_save_user_regs for abort/prefetch/undef/swi ...
401 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
404 .macro bad_save_user_regs
405 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
407 stmia sp, {r0 - r12} @ Save user registers (now in
409 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
411 ldmia r2, {r2 - r3} @ get values for "aborted" pc
412 @ and cpsr (into parm regs)
413 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
417 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
418 mov r0, sp @ save current stack into r0
422 .macro irq_save_user_regs
423 sub sp, sp, #S_FRAME_SIZE
424 stmia sp, {r0 - r12} @ Calling r0-r12
425 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
426 @ a reserved stack spot would
428 stmdb r8, {sp, lr}^ @ Calling SP, LR
429 str lr, [r8, #0] @ Save calling PC
431 str r6, [r8, #4] @ Save CPSR
432 str r0, [r8, #8] @ Save OLD_R0
436 .macro irq_restore_user_regs
437 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
439 ldr lr, [sp, #S_PC] @ Get PC
440 add sp, sp, #S_FRAME_SIZE
441 subs pc, lr, #4 @ return & move spsr_svc into
446 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
449 str lr, [r13] @ save caller lr in position 0
451 mrs lr, spsr @ get the spsr
452 str lr, [r13, #4] @ save spsr in position 1 of
455 mov r13, #MODE_SVC @ prepare SVC-Mode
457 msr spsr, r13 @ switch modes, make sure
459 mov lr, pc @ capture return pc
460 movs pc, lr @ jump to next instruction &
464 .macro get_bad_stack_swi
465 sub r13, r13, #4 @ space on current stack for
467 str r0, [r13] @ save R0's value.
468 ldr r0, IRQ_STACK_START_IN @ get data regions start
469 @ spots for abort stack
470 str lr, [r0] @ save caller lr in position 0
472 mrs r0, spsr @ get the spsr
473 str lr, [r0, #4] @ save spsr in position 1 of
475 ldr r0, [r13] @ restore r0
476 add r13, r13, #4 @ pop stack entry
479 .macro get_irq_stack @ setup IRQ stack
480 ldr sp, IRQ_STACK_START
483 .macro get_fiq_stack @ setup FIQ stack
484 ldr sp, FIQ_STACK_START
491 undefined_instruction:
494 bl do_undefined_instruction
500 bl do_software_interrupt
520 #ifdef CONFIG_USE_IRQ
527 irq_restore_user_regs
532 /* someone ought to write a more effective fiq_save_user_regs */
535 irq_restore_user_regs
551 #endif /* CONFIG_USE_IRQ */
552 #endif /* CONFIG_SPL_BUILD */