2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm-offsets.h>
19 #include <asm/system.h>
20 #include <linux/linkage.h>
22 /*************************************************************************
24 * Startup Code (reset vector)
26 * do important init only if we don't start from memory!
27 * setup Memory and board specific bits prior to relocation.
28 * relocate armboot to ram
31 *************************************************************************/
38 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
39 * except if in HYP mode already
42 and r1, r0, #0x1f @ mask mode bits
43 teq r1, #0x1a @ test for HYP mode
44 bicne r0, r0, #0x1f @ clear all mode bits
45 orrne r0, r0, #0x13 @ set SVC mode
46 orr r0, r0, #0xc0 @ disable FIQ and IRQ
51 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
52 * Continue to use ROM code vector only in OMAP4 spl)
54 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
55 /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
56 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
58 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
60 /* Set vector address in CP15 VBAR register */
62 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
65 /* the mask ROM code should have PLL and others stable */
66 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
73 /*------------------------------------------------------------------------------*/
75 ENTRY(c_runtime_cpu_setup)
77 * If I-cache is enabled invalidate it
79 #ifndef CONFIG_SYS_ICACHE_OFF
80 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
81 mcr p15, 0, r0, c7, c10, 4 @ DSB
82 mcr p15, 0, r0, c7, c5, 4 @ ISB
87 ENDPROC(c_runtime_cpu_setup)
89 /*************************************************************************
91 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
92 * __attribute__((weak));
94 * Stack pointer is not yet initialized at this moment
95 * Don't save anything to stack even if compiled with -O0
97 *************************************************************************/
98 ENTRY(save_boot_params)
99 bx lr @ back to my caller
100 ENDPROC(save_boot_params)
101 .weak save_boot_params
103 /*************************************************************************
107 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
108 * CONFIG_SYS_ICACHE_OFF is defined.
110 *************************************************************************/
115 mov r0, #0 @ set up for MCR
116 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
117 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
118 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
119 mcr p15, 0, r0, c7, c10, 4 @ DSB
120 mcr p15, 0, r0, c7, c5, 4 @ ISB
123 * disable MMU stuff and caches
125 mrc p15, 0, r0, c1, c0, 0
126 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
127 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
128 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
129 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
130 #ifdef CONFIG_SYS_ICACHE_OFF
131 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
133 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
135 mcr p15, 0, r0, c1, c0, 0
137 #ifdef CONFIG_ARM_ERRATA_716044
138 mrc p15, 0, r0, c1, c0, 0 @ read system control register
139 orr r0, r0, #1 << 11 @ set bit #11
140 mcr p15, 0, r0, c1, c0, 0 @ write system control register
143 #if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
144 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
145 orr r0, r0, #1 << 4 @ set bit #4
146 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
149 #ifdef CONFIG_ARM_ERRATA_743622
150 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
151 orr r0, r0, #1 << 6 @ set bit #6
152 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
155 #ifdef CONFIG_ARM_ERRATA_751472
156 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
157 orr r0, r0, #1 << 11 @ set bit #11
158 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
160 #ifdef CONFIG_ARM_ERRATA_761320
161 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
162 orr r0, r0, #1 << 21 @ set bit #21
163 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
166 mov pc, lr @ back to my caller
167 ENDPROC(cpu_init_cp15)
169 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
170 /*************************************************************************
172 * CPU_init_critical registers
174 * setup important registers
175 * setup memory timing
177 *************************************************************************/
180 * Jump to board specific initialization...
181 * The Mask ROM will have already initialized
182 * basic memory. Go here to bump up clock rate and handle
183 * wake up conditions.
185 b lowlevel_init @ go setup pll,mux,memory
186 ENDPROC(cpu_init_crit)