3 * Andre Przywara, Linaro <andre.przywara@linaro.org>
5 * Routines to transition ARMv7 processors from secure into non-secure state
6 * and from non-secure SVC into HYP mode
7 * needed to enable ARMv7 virtualization for current hypervisors
9 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/armv7.h>
16 #include <asm/secure.h>
18 static unsigned int read_id_pfr1(void)
22 asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg));
26 static unsigned long get_gicd_base_address(void)
28 #ifdef CONFIG_ARM_GIC_BASE_ADDRESS
29 return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
33 /* get the GIC base address from the CBAR register */
34 asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
36 /* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to
37 * encode this). Bail out here since we cannot access this without
40 if ((periphbase & 0xff) != 0) {
41 printf("nonsec: PERIPHBASE is above 4 GB, no access.\n");
45 return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET;
49 static void relocate_secure_section(void)
51 #ifdef CONFIG_ARMV7_SECURE_BASE
52 size_t sz = __secure_end - __secure_start;
54 memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz);
55 flush_dcache_range(CONFIG_ARMV7_SECURE_BASE,
56 CONFIG_ARMV7_SECURE_BASE + sz + 1);
57 invalidate_icache_all();
61 static void kick_secondary_cpus_gic(unsigned long gicdaddr)
63 /* kick all CPUs (except this one) by writing to GICD_SGIR */
64 writel(1U << 24, gicdaddr + GICD_SGIR);
67 void __weak smp_kick_all_cpus(void)
69 unsigned long gic_dist_addr;
71 gic_dist_addr = get_gicd_base_address();
72 if (gic_dist_addr == -1)
75 kick_secondary_cpus_gic(gic_dist_addr);
78 int armv7_init_nonsec(void)
81 unsigned itlinesnr, i;
82 unsigned long gic_dist_addr;
84 /* check whether the CPU supports the security extensions */
86 if ((reg & 0xF0) == 0) {
87 printf("nonsec: Security extensions not implemented.\n");
91 /* the SCR register will be set directly in the monitor mode handler,
92 * according to the spec one should not tinker with it in secure state
93 * in SVC mode. Do not try to read it once in non-secure state,
94 * any access to it will trap.
97 gic_dist_addr = get_gicd_base_address();
98 if (gic_dist_addr == -1)
101 /* enable the GIC distributor */
102 writel(readl(gic_dist_addr + GICD_CTLR) | 0x03,
103 gic_dist_addr + GICD_CTLR);
105 /* TYPER[4:0] contains an encoded number of available interrupts */
106 itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f;
108 /* set all bits in the GIC group registers to one to allow access
109 * from non-secure state. The first 32 interrupts are private per
110 * CPU and will be set later when enabling the GIC for each core
112 for (i = 1; i <= itlinesnr; i++)
113 writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
115 #ifndef CONFIG_ARMV7_PSCI
116 smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
120 /* call the non-sec switching code on this CPU also */
121 relocate_secure_section();
122 secure_ram_addr(_nonsec_init)();