3 * David Feng <fenghua@phytium.com.cn>
5 * This file is based on sample code from ARMv8 ARM.
7 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm-offsets.h>
13 #include <asm/macro.h>
14 #include <linux/linkage.h>
17 * void __asm_flush_dcache_level(level)
19 * clean and invalidate one level cache.
22 * x1: 0 flush & invalidate, 1 invalidate only
25 ENTRY(__asm_flush_dcache_level)
27 msr csselr_el1, x12 /* select cache level */
28 isb /* sync change of cssidr_el1 */
29 mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
30 and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
31 add x2, x2, #4 /* x2 <- log2(cache line size) */
33 and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
35 sub w4, w4, 1 /* round up log2(#ways + 1) */
36 clz w5, w4 /* bit position of #ways */
38 and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
39 /* x12 <- cache level << 1 */
40 /* x2 <- line length offset */
41 /* x3 <- number of cache ways - 1 */
42 /* x4 <- number of cache sets - 1 */
43 /* x5 <- bit position of #ways */
46 mov x6, x3 /* x6 <- working copy of #ways */
49 orr x9, x12, x7 /* map way and level to cisw value */
51 orr x9, x9, x7 /* map set number to cisw value */
55 1: dc cisw, x9 /* clean & invalidate by set/way */
56 2: subs x6, x6, #1 /* decrement the way */
58 subs x4, x4, #1 /* decrement the set */
62 ENDPROC(__asm_flush_dcache_level)
65 * void __asm_flush_dcache_all(int invalidate_only)
67 * x0: 0 flush & invalidate, 1 invalidate only
69 * clean and invalidate all data cache by SET/WAY.
71 ENTRY(__asm_dcache_all)
74 mrs x10, clidr_el1 /* read clidr_el1 */
76 and x11, x11, #0x7 /* x11 <- loc */
77 cbz x11, finished /* if loc is 0, exit */
79 mov x0, #0 /* start flush at cache level 0 */
80 /* x0 <- cache level */
81 /* x10 <- clidr_el1 */
83 /* x15 <- return address */
87 add x12, x12, x0 /* x0 <- tripled cache level */
89 and x12, x12, #7 /* x12 <- cache type */
91 b.lt skip /* skip if no cache or icache */
92 bl __asm_flush_dcache_level /* x1 = 0 flush, 1 invalidate */
94 add x0, x0, #1 /* increment cache level */
99 msr csselr_el1, x0 /* resotre csselr_el1 */
106 ENDPROC(__asm_dcache_all)
108 ENTRY(__asm_flush_dcache_all)
114 ENDPROC(__asm_flush_dcache_all)
116 ENTRY(__asm_invalidate_dcache_all)
122 ENDPROC(__asm_invalidate_dcache_all)
125 * void __asm_flush_dcache_range(start, end)
127 * clean & invalidate data cache in the range
132 ENTRY(__asm_flush_dcache_range)
137 lsl x2, x2, x3 /* cache line size */
139 /* x2 <- minimal cache line size in cache system */
142 1: dc civac, x0 /* clean & invalidate data or unified cache */
148 ENDPROC(__asm_flush_dcache_range)
151 * void __asm_invalidate_icache_all(void)
153 * invalidate all tlb entries.
155 ENTRY(__asm_invalidate_icache_all)
159 ENDPROC(__asm_invalidate_icache_all)