5 select SYS_FSL_ERRATUM_A010315
10 select SYS_FSL_ERRATUM_A010315
11 select SYS_FSL_ERRATUM_A010539
16 select SYS_FSL_ERRATUM_A010539
22 select SYS_FSL_HAS_DP_DDR
35 menu "Layerscape architecture"
36 depends on FSL_LSCH2 || FSL_LSCH3
41 config SYS_FSL_ERRATUM_A010315
42 bool "Workaround for PCIe erratum A010315"
44 config SYS_FSL_ERRATUM_A010539
45 bool "Workaround for PIN MUX erratum A010539"
48 int "Maximum number of CPUs permitted for Layerscape"
49 default 4 if ARCH_LS1043A
50 default 4 if ARCH_LS1046A
51 default 16 if ARCH_LS2080A
54 Set this number to the maximum number of possible CPUs in the SoC.
55 SoCs may have multiple clusters with each cluster may have multiple
56 ports. If some ports are reserved but higher ports are used for
57 cores, count the reserved ports. This will allocate enough memory
58 in spin table to properly handle all cores.
60 config NUM_DDR_CONTROLLERS
61 int "Maximum DDR controllers"
62 default 3 if ARCH_LS2080A
65 config SYS_FSL_IFC_BANK_COUNT
66 int "Maximum banks of Integrated flash controller"
67 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
68 default 4 if ARCH_LS1043A
69 default 4 if ARCH_LS1046A
70 default 8 if ARCH_LS2080A
72 config SYS_FSL_HAS_DP_DDR