7 select SYS_FSL_ERRATUM_A010315
8 select SYS_FSL_ERRATUM_A009798
9 select SYS_FSL_ERRATUM_A008997
10 select SYS_FSL_ERRATUM_A009007
11 select SYS_FSL_ERRATUM_A009008
12 select ARCH_EARLY_INIT_R
13 select BOARD_EARLY_INIT_F
18 select ARMV8_SET_SMPEN
22 select SYS_FSL_DDR_VER_50
23 select SYS_FSL_ERRATUM_A008850
24 select SYS_FSL_ERRATUM_A008997
25 select SYS_FSL_ERRATUM_A009007
26 select SYS_FSL_ERRATUM_A009008
27 select SYS_FSL_ERRATUM_A009660
28 select SYS_FSL_ERRATUM_A009663
29 select SYS_FSL_ERRATUM_A009798
30 select SYS_FSL_ERRATUM_A009929
31 select SYS_FSL_ERRATUM_A009942
32 select SYS_FSL_ERRATUM_A010315
33 select SYS_FSL_ERRATUM_A010539
34 select SYS_FSL_HAS_DDR3
35 select SYS_FSL_HAS_DDR4
36 select ARCH_EARLY_INIT_R
37 select BOARD_EARLY_INIT_F
44 select ARMV8_SET_SMPEN
48 select SYS_FSL_DDR_VER_50
49 select SYS_FSL_ERRATUM_A008336
50 select SYS_FSL_ERRATUM_A008511
51 select SYS_FSL_ERRATUM_A008850
52 select SYS_FSL_ERRATUM_A008997
53 select SYS_FSL_ERRATUM_A009007
54 select SYS_FSL_ERRATUM_A009008
55 select SYS_FSL_ERRATUM_A009798
56 select SYS_FSL_ERRATUM_A009801
57 select SYS_FSL_ERRATUM_A009803
58 select SYS_FSL_ERRATUM_A009942
59 select SYS_FSL_ERRATUM_A010165
60 select SYS_FSL_ERRATUM_A010539
61 select SYS_FSL_HAS_DDR4
63 select ARCH_EARLY_INIT_R
64 select BOARD_EARLY_INIT_F
70 select ARMV8_SET_SMPEN
74 select SYS_FSL_DDR_VER_50
77 select SYS_FSL_ERRATUM_A009803
78 select SYS_FSL_ERRATUM_A009942
79 select SYS_FSL_ERRATUM_A010165
80 select SYS_FSL_ERRATUM_A008511
81 select SYS_FSL_ERRATUM_A008850
82 select SYS_FSL_ERRATUM_A009007
83 select SYS_FSL_HAS_CCI400
84 select SYS_FSL_HAS_DDR4
85 select SYS_FSL_HAS_RGMII
86 select SYS_FSL_HAS_SEC
87 select SYS_FSL_SEC_COMPAT_5
92 select ARCH_EARLY_INIT_R
93 select BOARD_EARLY_INIT_F
99 select ARMV8_SET_SMPEN
100 select ARM_ERRATA_826974
101 select ARM_ERRATA_828024
102 select ARM_ERRATA_829520
103 select ARM_ERRATA_833471
106 select SYS_FSL_DDR_LE
107 select SYS_FSL_DDR_VER_50
108 select SYS_FSL_HAS_CCN504
109 select SYS_FSL_HAS_DP_DDR
110 select SYS_FSL_HAS_SEC
111 select SYS_FSL_HAS_DDR4
112 select SYS_FSL_SEC_COMPAT_5
113 select SYS_FSL_SEC_LE
114 select SYS_FSL_SRDS_2
117 select SYS_FSL_ERRATUM_A008336
118 select SYS_FSL_ERRATUM_A008511
119 select SYS_FSL_ERRATUM_A008514
120 select SYS_FSL_ERRATUM_A008585
121 select SYS_FSL_ERRATUM_A008997
122 select SYS_FSL_ERRATUM_A009007
123 select SYS_FSL_ERRATUM_A009008
124 select SYS_FSL_ERRATUM_A009635
125 select SYS_FSL_ERRATUM_A009663
126 select SYS_FSL_ERRATUM_A009798
127 select SYS_FSL_ERRATUM_A009801
128 select SYS_FSL_ERRATUM_A009803
129 select SYS_FSL_ERRATUM_A009942
130 select SYS_FSL_ERRATUM_A010165
131 select SYS_FSL_ERRATUM_A009203
132 select ARCH_EARLY_INIT_R
133 select BOARD_EARLY_INIT_F
138 select SYS_FSL_HAS_CCI400
139 select SYS_FSL_HAS_SEC
140 select SYS_FSL_SEC_COMPAT_5
141 select SYS_FSL_SEC_BE
142 select SYS_FSL_SRDS_1
143 select SYS_HAS_SERDES
147 select SYS_FSL_SRDS_1
148 select SYS_HAS_SERDES
151 bool "Management Complex network"
152 depends on ARCH_LS2080A || ARCH_LS1088A
156 Enable Management Complex (MC) network
158 menu "Layerscape architecture"
159 depends on FSL_LSCH2 || FSL_LSCH3
161 config FSL_PCIE_COMPAT
162 string "PCIe compatible of Kernel DT"
163 depends on PCIE_LAYERSCAPE
164 default "fsl,ls1012a-pcie" if ARCH_LS1012A
165 default "fsl,ls1043a-pcie" if ARCH_LS1043A
166 default "fsl,ls1046a-pcie" if ARCH_LS1046A
167 default "fsl,ls2080a-pcie" if ARCH_LS2080A
168 default "fsl,ls1088a-pcie" if ARCH_LS1088A
170 This compatible is used to find pci controller node in Kernel DT
173 config HAS_FEATURE_GIC64K_ALIGN
175 default y if ARCH_LS1043A
177 config HAS_FEATURE_ENHANCED_MSI
179 default y if ARCH_LS1043A
181 menu "Layerscape PPA"
183 bool "FSL Layerscape PPA firmware support"
184 depends on !ARMV8_PSCI
185 select ARMV8_SEC_FIRMWARE_SUPPORT
186 select SEC_FIRMWARE_ARMV8_PSCI
187 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
189 The FSL Primary Protected Application (PPA) is a software component
190 which is loaded during boot stage, and then remains resident in RAM
191 and runs in the TrustZone after boot.
194 config SPL_FSL_LS_PPA
195 bool "FSL Layerscape PPA firmware support for SPL build"
196 depends on !ARMV8_PSCI
197 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
198 select SEC_FIRMWARE_ARMV8_PSCI
199 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
201 The FSL Primary Protected Application (PPA) is a software component
202 which is loaded during boot stage, and then remains resident in RAM
203 and runs in the TrustZone after boot. This is to load PPA during SPL
204 stage instead of the RAM version of U-Boot. Once PPA is initialized,
205 the rest of U-Boot (including RAM version) runs at EL2.
207 prompt "FSL Layerscape PPA firmware loading-media select"
208 depends on FSL_LS_PPA
209 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
210 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
211 default SYS_LS_PPA_FW_IN_XIP
213 config SYS_LS_PPA_FW_IN_XIP
216 Say Y here if the PPA firmware locate at XIP flash, such
217 as NOR or QSPI flash.
219 config SYS_LS_PPA_FW_IN_MMC
220 bool "eMMC or SD Card"
222 Say Y here if the PPA firmware locate at eMMC/SD card.
224 config SYS_LS_PPA_FW_IN_NAND
227 Say Y here if the PPA firmware locate at NAND flash.
231 config SYS_LS_PPA_FW_ADDR
232 hex "Address of PPA firmware loading from"
233 depends on FSL_LS_PPA
234 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
235 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
236 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
237 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
238 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
239 default 0x400000 if SYS_LS_PPA_FW_IN_MMC
240 default 0x400000 if SYS_LS_PPA_FW_IN_NAND
243 If the PPA firmware locate at XIP flash, such as NOR or
244 QSPI flash, this address is a directly memory-mapped.
245 If it is in a serial accessed flash, such as NAND and SD
246 card, it is a byte offset.
248 config SYS_LS_PPA_ESBC_ADDR
249 hex "hdr address of PPA firmware loading from"
250 depends on FSL_LS_PPA && CHAIN_OF_TRUST
251 default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
252 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
253 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
254 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
255 default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
256 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
257 default 0x680000 if SYS_LS_PPA_FW_IN_MMC
258 default 0x680000 if SYS_LS_PPA_FW_IN_NAND
260 If the PPA header firmware locate at XIP flash, such as NOR or
261 QSPI flash, this address is a directly memory-mapped.
262 If it is in a serial accessed flash, such as NAND and SD
263 card, it is a byte offset.
265 config LS_PPA_ESBC_HDR_SIZE
266 hex "Length of PPA ESBC header"
267 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
270 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
271 NAND to memory to validate PPA image.
275 config SYS_FSL_ERRATUM_A008997
276 bool "Workaround for USB PHY erratum A008997"
278 config SYS_FSL_ERRATUM_A009007
281 Workaround for USB PHY erratum A009007
283 config SYS_FSL_ERRATUM_A009008
284 bool "Workaround for USB PHY erratum A009008"
286 config SYS_FSL_ERRATUM_A009798
287 bool "Workaround for USB PHY erratum A009798"
289 config SYS_FSL_ERRATUM_A010315
290 bool "Workaround for PCIe erratum A010315"
292 config SYS_FSL_ERRATUM_A010539
293 bool "Workaround for PIN MUX erratum A010539"
296 int "Maximum number of CPUs permitted for Layerscape"
297 default 4 if ARCH_LS1043A
298 default 4 if ARCH_LS1046A
299 default 16 if ARCH_LS2080A
300 default 8 if ARCH_LS1088A
303 Set this number to the maximum number of possible CPUs in the SoC.
304 SoCs may have multiple clusters with each cluster may have multiple
305 ports. If some ports are reserved but higher ports are used for
306 cores, count the reserved ports. This will allocate enough memory
307 in spin table to properly handle all cores.
312 Enable Freescale Secure Boot feature
315 bool "Init the QSPI AHB bus"
317 The default setting for QSPI AHB bus just support 3bytes addressing.
318 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
319 bus for those flashes to support the full QSPI flash size.
321 config SYS_CCI400_OFFSET
322 hex "Offset for CCI400 base"
323 depends on SYS_FSL_HAS_CCI400
324 default 0x3090000 if ARCH_LS1088A
325 default 0x180000 if FSL_LSCH2
327 Offset for CCI400 base
328 CCI400 base addr = CCSRBAR + CCI400_OFFSET
330 config SYS_FSL_IFC_BANK_COUNT
331 int "Maximum banks of Integrated flash controller"
332 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
333 default 4 if ARCH_LS1043A
334 default 4 if ARCH_LS1046A
335 default 8 if ARCH_LS2080A || ARCH_LS1088A
337 config SYS_FSL_HAS_CCI400
340 config SYS_FSL_HAS_CCN504
343 config SYS_FSL_HAS_DP_DDR
346 config SYS_FSL_SRDS_1
349 config SYS_FSL_SRDS_2
352 config SYS_HAS_SERDES
363 menu "Layerscape clock tree configuration"
364 depends on FSL_LSCH2 || FSL_LSCH3
367 bool "Enable clock tree initialization"
370 config CLUSTER_CLK_FREQ
371 int "Reference clock of core cluster"
372 depends on ARCH_LS1012A
375 This number is the reference clock frequency of core PLL.
376 For most platforms, the core PLL and Platform PLL have the same
377 reference clock, but for some platforms, LS1012A for instance,
378 they are provided sepatately.
380 config SYS_FSL_PCLK_DIV
381 int "Platform clock divider"
382 default 1 if ARCH_LS1043A
383 default 1 if ARCH_LS1046A
384 default 1 if ARCH_LS1088A
387 This is the divider that is used to derive Platform clock from
388 Platform PLL, in another word:
389 Platform_clk = Platform_PLL_freq / this_divider
391 config SYS_FSL_DSPI_CLK_DIV
392 int "DSPI clock divider"
393 default 1 if ARCH_LS1043A
396 This is the divider that is used to derive DSPI clock from Platform
397 clock, in another word DSPI_clk = Platform_clk / this_divider.
399 config SYS_FSL_DUART_CLK_DIV
400 int "DUART clock divider"
401 default 1 if ARCH_LS1043A
404 This is the divider that is used to derive DUART clock from Platform
405 clock, in another word DUART_clk = Platform_clk / this_divider.
407 config SYS_FSL_I2C_CLK_DIV
408 int "I2C clock divider"
409 default 1 if ARCH_LS1043A
412 This is the divider that is used to derive I2C clock from Platform
413 clock, in another word I2C_clk = Platform_clk / this_divider.
415 config SYS_FSL_IFC_CLK_DIV
416 int "IFC clock divider"
417 default 1 if ARCH_LS1043A
420 This is the divider that is used to derive IFC clock from Platform
421 clock, in another word IFC_clk = Platform_clk / this_divider.
423 config SYS_FSL_LPUART_CLK_DIV
424 int "LPUART clock divider"
425 default 1 if ARCH_LS1043A
428 This is the divider that is used to derive LPUART clock from Platform
429 clock, in another word LPUART_clk = Platform_clk / this_divider.
431 config SYS_FSL_SDHC_CLK_DIV
432 int "SDHC clock divider"
433 default 1 if ARCH_LS1043A
434 default 1 if ARCH_LS1012A
437 This is the divider that is used to derive SDHC clock from Platform
438 clock, in another word SDHC_clk = Platform_clk / this_divider.
444 Reserve memory from the top, tracked by gd->arch.resv_ram. This
445 reserved RAM can be used by special driver that resides in memory
446 after U-Boot exits. It's up to implementation to allocate and allow
447 access to this reserved memory. For example, the reserved RAM can
448 be at the high end of physical memory. The reserve RAM may be
449 excluded from memory bank(s) passed to OS, or marked as reserved.
454 Ethernet controller 1, this is connected to MAC3.
455 Provides DPAA2 capabilities
460 Ethernet controller 2, this is connected to MAC4.
461 Provides DPAA2 capabilities
463 config SYS_FSL_ERRATUM_A008336
466 config SYS_FSL_ERRATUM_A008514
469 config SYS_FSL_ERRATUM_A008585
472 config SYS_FSL_ERRATUM_A008850
475 config SYS_FSL_ERRATUM_A009203
478 config SYS_FSL_ERRATUM_A009635
481 config SYS_FSL_ERRATUM_A009660
484 config SYS_FSL_ERRATUM_A009929
488 config SYS_FSL_HAS_RGMII
490 depends on SYS_FSL_EC1 || SYS_FSL_EC2
493 config SYS_MC_RSV_MEM_ALIGN
494 hex "Management Complex reserved memory alignment"
496 default 0x20000000 if ARCH_LS2080A
497 default 0x70000000 if ARCH_LS1088A
499 Reserved memory needs to be aligned for MC to use. Default value
503 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
505 config HAS_FSL_XHCI_USB
507 default y if ARCH_LS1043A || ARCH_LS1046A
509 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
510 pins, select it when the pins are assigned to USB.