7 select SYS_FSL_ERRATUM_A010315
8 select ARCH_EARLY_INIT_R
9 select BOARD_EARLY_INIT_F
13 select ARMV8_SET_SMPEN
17 select SYS_FSL_DDR_VER_50
18 select SYS_FSL_ERRATUM_A008850
19 select SYS_FSL_ERRATUM_A009660
20 select SYS_FSL_ERRATUM_A009663
21 select SYS_FSL_ERRATUM_A009929
22 select SYS_FSL_ERRATUM_A009942
23 select SYS_FSL_ERRATUM_A010315
24 select SYS_FSL_ERRATUM_A010539
25 select SYS_FSL_HAS_DDR3
26 select SYS_FSL_HAS_DDR4
27 select ARCH_EARLY_INIT_R
28 select BOARD_EARLY_INIT_F
32 select ARMV8_SET_SMPEN
36 select SYS_FSL_DDR_VER_50
37 select SYS_FSL_ERRATUM_A008336
38 select SYS_FSL_ERRATUM_A008511
39 select SYS_FSL_ERRATUM_A009801
40 select SYS_FSL_ERRATUM_A009803
41 select SYS_FSL_ERRATUM_A009942
42 select SYS_FSL_ERRATUM_A010165
43 select SYS_FSL_ERRATUM_A010539
44 select SYS_FSL_HAS_DDR4
46 select ARCH_EARLY_INIT_R
47 select BOARD_EARLY_INIT_F
51 select ARMV8_SET_SMPEN
52 select ARM_ERRATA_826974
53 select ARM_ERRATA_828024
54 select ARM_ERRATA_829520
55 select ARM_ERRATA_833471
59 select SYS_FSL_DDR_VER_50
60 select SYS_FSL_HAS_DP_DDR
61 select SYS_FSL_HAS_SEC
62 select SYS_FSL_HAS_DDR4
63 select SYS_FSL_SEC_COMPAT_5
66 select SYS_FSL_ERRATUM_A008336
67 select SYS_FSL_ERRATUM_A008511
68 select SYS_FSL_ERRATUM_A008514
69 select SYS_FSL_ERRATUM_A008585
70 select SYS_FSL_ERRATUM_A009635
71 select SYS_FSL_ERRATUM_A009663
72 select SYS_FSL_ERRATUM_A009801
73 select SYS_FSL_ERRATUM_A009803
74 select SYS_FSL_ERRATUM_A009942
75 select SYS_FSL_ERRATUM_A010165
76 select ARCH_EARLY_INIT_R
77 select BOARD_EARLY_INIT_F
81 select SYS_FSL_HAS_SEC
82 select SYS_FSL_SEC_COMPAT_5
92 menu "Layerscape architecture"
93 depends on FSL_LSCH2 || FSL_LSCH3
95 config FSL_PCIE_COMPAT
96 string "PCIe compatible of Kernel DT"
97 depends on PCIE_LAYERSCAPE
98 default "fsl,ls1012a-pcie" if ARCH_LS1012A
99 default "fsl,ls1043a-pcie" if ARCH_LS1043A
100 default "fsl,ls1046a-pcie" if ARCH_LS1046A
101 default "fsl,ls2080a-pcie" if ARCH_LS2080A
103 This compatible is used to find pci controller node in Kernel DT
106 config HAS_FEATURE_GIC64K_ALIGN
108 default y if ARCH_LS1043A
110 config HAS_FEATURE_ENHANCED_MSI
112 default y if ARCH_LS1043A
114 menu "Layerscape PPA"
116 bool "FSL Layerscape PPA firmware support"
117 depends on !ARMV8_PSCI
118 select ARMV8_SEC_FIRMWARE_SUPPORT
119 select SEC_FIRMWARE_ARMV8_PSCI
120 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
122 The FSL Primary Protected Application (PPA) is a software component
123 which is loaded during boot stage, and then remains resident in RAM
124 and runs in the TrustZone after boot.
127 prompt "FSL Layerscape PPA firmware loading-media select"
128 depends on FSL_LS_PPA
129 default SYS_LS_PPA_FW_IN_XIP
131 config SYS_LS_PPA_FW_IN_XIP
134 Say Y here if the PPA firmware locate at XIP flash, such
135 as NOR or QSPI flash.
139 config SYS_LS_PPA_FW_ADDR
140 hex "Address of PPA firmware loading from"
141 depends on FSL_LS_PPA
142 default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
143 default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
145 If the PPA firmware locate at XIP flash, such as NOR or
146 QSPI flash, this address is a directly memory-mapped.
147 If it is in a serial accessed flash, such as NAND and SD
148 card, it is a byte offset.
151 config SYS_FSL_ERRATUM_A010315
152 bool "Workaround for PCIe erratum A010315"
154 config SYS_FSL_ERRATUM_A010539
155 bool "Workaround for PIN MUX erratum A010539"
158 int "Maximum number of CPUs permitted for Layerscape"
159 default 4 if ARCH_LS1043A
160 default 4 if ARCH_LS1046A
161 default 16 if ARCH_LS2080A
164 Set this number to the maximum number of possible CPUs in the SoC.
165 SoCs may have multiple clusters with each cluster may have multiple
166 ports. If some ports are reserved but higher ports are used for
167 cores, count the reserved ports. This will allocate enough memory
168 in spin table to properly handle all cores.
173 Enable Freescale Secure Boot feature
176 bool "Init the QSPI AHB bus"
178 The default setting for QSPI AHB bus just support 3bytes addressing.
179 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
180 bus for those flashes to support the full QSPI flash size.
182 config SYS_FSL_IFC_BANK_COUNT
183 int "Maximum banks of Integrated flash controller"
184 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
185 default 4 if ARCH_LS1043A
186 default 4 if ARCH_LS1046A
187 default 8 if ARCH_LS2080A
189 config SYS_FSL_HAS_DP_DDR
192 config SYS_FSL_SRDS_1
195 config SYS_FSL_SRDS_2
198 config SYS_HAS_SERDES
203 menu "Layerscape clock tree configuration"
204 depends on FSL_LSCH2 || FSL_LSCH3
207 bool "Enable clock tree initialization"
210 config CLUSTER_CLK_FREQ
211 int "Reference clock of core cluster"
212 depends on ARCH_LS1012A
215 This number is the reference clock frequency of core PLL.
216 For most platforms, the core PLL and Platform PLL have the same
217 reference clock, but for some platforms, LS1012A for instance,
218 they are provided sepatately.
220 config SYS_FSL_PCLK_DIV
221 int "Platform clock divider"
222 default 1 if ARCH_LS1043A
223 default 1 if ARCH_LS1046A
226 This is the divider that is used to derive Platform clock from
227 Platform PLL, in another word:
228 Platform_clk = Platform_PLL_freq / this_divider
230 config SYS_FSL_DSPI_CLK_DIV
231 int "DSPI clock divider"
232 default 1 if ARCH_LS1043A
235 This is the divider that is used to derive DSPI clock from Platform
236 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
238 config SYS_FSL_DUART_CLK_DIV
239 int "DUART clock divider"
240 default 1 if ARCH_LS1043A
243 This is the divider that is used to derive DUART clock from Platform
244 clock, in another word DUART_clk = Platform_clk / this_divider.
246 config SYS_FSL_I2C_CLK_DIV
247 int "I2C clock divider"
248 default 1 if ARCH_LS1043A
251 This is the divider that is used to derive I2C clock from Platform
252 clock, in another word I2C_clk = Platform_clk / this_divider.
254 config SYS_FSL_IFC_CLK_DIV
255 int "IFC clock divider"
256 default 1 if ARCH_LS1043A
259 This is the divider that is used to derive IFC clock from Platform
260 clock, in another word IFC_clk = Platform_clk / this_divider.
262 config SYS_FSL_LPUART_CLK_DIV
263 int "LPUART clock divider"
264 default 1 if ARCH_LS1043A
267 This is the divider that is used to derive LPUART clock from Platform
268 clock, in another word LPUART_clk = Platform_clk / this_divider.
270 config SYS_FSL_SDHC_CLK_DIV
271 int "SDHC clock divider"
272 default 1 if ARCH_LS1043A
273 default 1 if ARCH_LS1012A
276 This is the divider that is used to derive SDHC clock from Platform
277 clock, in another word SDHC_clk = Platform_clk / this_divider.
280 config SYS_FSL_ERRATUM_A008336
283 config SYS_FSL_ERRATUM_A008514
286 config SYS_FSL_ERRATUM_A008585
289 config SYS_FSL_ERRATUM_A008850
292 config SYS_FSL_ERRATUM_A009635
295 config SYS_FSL_ERRATUM_A009660
298 config SYS_FSL_ERRATUM_A009929