2 * Copyright 2014-2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/system.h>
11 #include <asm/armv8/mmu.h>
13 #include <asm/arch/fsl_serdes.h>
14 #include <asm/arch/soc.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/speed.h>
18 #include <asm/arch/mp.h>
21 #include <fsl_debug_server.h>
22 #include <fsl-mc/fsl_mc.h>
23 #ifdef CONFIG_FSL_ESDHC
24 #include <fsl_esdhc.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 struct mm_region *mem_map = early_map;
31 void cpu_name(char *name)
33 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
34 unsigned int i, svr, ver;
36 svr = gur_in32(&gur->svr);
37 ver = SVR_SOC_VER(svr);
39 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
40 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
41 strcpy(name, cpu_type_list[i].name);
43 if (IS_E_PROCESSOR(svr))
48 if (i == ARRAY_SIZE(cpu_type_list))
49 strcpy(name, "unknown");
52 #ifndef CONFIG_SYS_DCACHE_OFF
54 * To start MMU before DDR is available, we create MMU table in SRAM.
55 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
56 * levels of translation tables here to cover 40-bit address space.
57 * We use 4KB granule size, with 40 bits physical address, T0SZ=24
58 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
59 * Note, the debug print in cache_v8.c is not usable for debugging
60 * these early MMU tables because UART is not yet available.
62 static inline void early_mmu_setup(void)
64 unsigned int el = current_el();
66 /* global data is already setup, no allocation yet */
67 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
68 gd->arch.tlb_fillptr = gd->arch.tlb_addr;
69 gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
71 /* Create early page tables */
74 /* point TTBR to the new table */
75 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
76 get_tcr(el, NULL, NULL) &
77 ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
80 set_sctlr(get_sctlr() | CR_M);
84 * The final tables look similar to early tables, but different in detail.
85 * These tables are in DRAM. Sub tables are added to enable cache for
88 * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
89 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
91 static inline void final_mmu_setup(void)
93 u64 tlb_addr_save = gd->arch.tlb_addr;
94 unsigned int el = current_el();
95 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
101 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
102 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
105 * Only use gd->arch.secure_ram if the address is
106 * recalculated. Align to 4KB for MMU table.
108 /* put page tables in secure ram */
109 index = ARRAY_SIZE(final_map) - 2;
110 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
111 final_map[index].virt = gd->arch.secure_ram & ~0x3;
112 final_map[index].phys = final_map[index].virt;
113 final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
114 final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
115 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
116 tlb_addr_save = gd->arch.tlb_addr;
118 /* Use allocated (board_f.c) memory for TLB */
119 tlb_addr_save = gd->arch.tlb_allocated;
120 gd->arch.tlb_addr = tlb_addr_save;
125 /* Reset the fill ptr */
126 gd->arch.tlb_fillptr = tlb_addr_save;
128 /* Create normal system page tables */
131 /* Create emergency page tables */
132 gd->arch.tlb_addr = gd->arch.tlb_fillptr;
133 gd->arch.tlb_emerg = gd->arch.tlb_addr;
135 gd->arch.tlb_addr = tlb_addr_save;
137 /* flush new MMU table */
138 flush_dcache_range(gd->arch.tlb_addr,
139 gd->arch.tlb_addr + gd->arch.tlb_size);
141 /* point TTBR to the new table */
142 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
145 * MMU is already enabled, just need to invalidate TLB to load the
146 * new table. The new table is compatible with the current table, if
147 * MMU somehow walks through the new table before invalidation TLB,
148 * it still works. So we don't need to turn off MMU here.
152 u64 get_page_table_size(void)
157 int arch_cpu_init(void)
160 __asm_invalidate_dcache_all();
161 __asm_invalidate_tlb_all();
163 set_sctlr(get_sctlr() | CR_C);
168 * This function is called from lib/board.c.
169 * It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
170 * There is no need to disable d-cache for this operation.
172 void enable_caches(void)
175 __asm_invalidate_tlb_all();
179 static inline u32 initiator_type(u32 cluster, int init_id)
181 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
182 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
185 type = gur_in32(&gur->tp_ityp[idx]);
186 if (type & TP_ITYP_AV)
194 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
195 int i = 0, count = 0;
196 u32 cluster, type, mask = 0;
201 cluster = gur_in32(&gur->tp_cluster[i].lower);
202 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
203 type = initiator_type(cluster, j);
205 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
211 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
217 * Return the number of cores on this SOC.
219 int cpu_numcores(void)
221 return hweight32(cpu_mask());
224 int fsl_qoriq_core_to_cluster(unsigned int core)
226 struct ccsr_gur __iomem *gur =
227 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
228 int i = 0, count = 0;
234 cluster = gur_in32(&gur->tp_cluster[i].lower);
235 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
236 if (initiator_type(cluster, j)) {
243 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
245 return -1; /* cannot identify the cluster */
248 u32 fsl_qoriq_core_to_type(unsigned int core)
250 struct ccsr_gur __iomem *gur =
251 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
252 int i = 0, count = 0;
258 cluster = gur_in32(&gur->tp_cluster[i].lower);
259 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
260 type = initiator_type(cluster, j);
268 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
270 return -1; /* cannot identify the cluster */
275 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
277 return gur_in32(&gur->svr);
280 #ifdef CONFIG_DISPLAY_CPUINFO
281 int print_cpuinfo(void)
283 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
284 struct sys_info sysinfo;
286 unsigned int i, core;
287 u32 type, rcw, svr = gur_in32(&gur->svr);
292 printf(" %s (0x%x)\n", buf, svr);
293 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
294 get_sys_info(&sysinfo);
295 puts("Clock Configuration:");
296 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
299 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
300 printf("CPU%d(%s):%-4s MHz ", core,
301 type == TY_ITYP_VER_A7 ? "A7 " :
302 (type == TY_ITYP_VER_A53 ? "A53" :
303 (type == TY_ITYP_VER_A57 ? "A57" : " ")),
304 strmhz(buf, sysinfo.freq_processor[core]));
306 printf("\n Bus: %-4s MHz ",
307 strmhz(buf, sysinfo.freq_systembus));
308 printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
309 #ifdef CONFIG_SYS_DPAA_FMAN
310 printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
312 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
313 if (soc_has_dp_ddr()) {
314 printf(" DP-DDR: %-4s MT/s",
315 strmhz(buf, sysinfo.freq_ddrbus2));
321 * Display the RCW, so that no one gets confused as to what RCW
322 * we're actually using for this boot.
324 puts("Reset Configuration Word (RCW):");
325 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
326 rcw = gur_in32(&gur->rcwsr[i]);
328 printf("\n %08x:", i * 4);
329 printf(" %08x", rcw);
337 #ifdef CONFIG_FSL_ESDHC
338 int cpu_mmc_init(bd_t *bis)
340 return fsl_esdhc_mmc_init(bis);
344 int cpu_eth_init(bd_t *bis)
348 #ifdef CONFIG_FSL_MC_ENET
349 error = fsl_mc_ldpaa_init(bis);
351 #ifdef CONFIG_FMAN_ENET
352 fm_standard_init(bis);
357 int arch_early_init_r(void)
363 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
368 rv = fsl_layerscape_wake_seconday_cores();
370 printf("Did not wake secondary cores\n");
373 #ifdef CONFIG_SYS_HAS_SERDES
376 #ifdef CONFIG_FMAN_ENET
384 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
385 #ifdef CONFIG_FSL_LSCH3
386 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
388 #ifdef CONFIG_LS2080A
389 u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
391 #ifdef COUNTER_FREQUENCY_REAL
392 unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
394 /* Update with accurate clock frequency */
395 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
398 #ifdef CONFIG_FSL_LSCH3
399 /* Enable timebase for all clusters.
400 * It is safe to do so even some clusters are not enabled.
402 out_le32(cltbenr, 0xf);
405 #ifdef CONFIG_LS2080A
407 * In certain Layerscape SoCs, the clock for each core's
408 * has an enable bit in the PMU Physical Core Time Base Enable
409 * Register (PCTBENR), which allows the watchdog to operate.
411 setbits_le32(pctbenr, 0xff);
414 /* Enable clock for timer
415 * This is a global setting.
417 out_le32(cntcr, 0x1);
422 void reset_cpu(ulong addr)
424 u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
427 /* Raise RESET_REQ_B */
428 val = scfg_in32(rstcr);
430 scfg_out32(rstcr, val);
433 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
435 phys_size_t ram_top = ram_size;
437 #ifdef CONFIG_SYS_MEM_TOP_HIDE
438 #error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function
440 /* Carve the Debug Server private DRAM block from the end of DRAM */
441 #ifdef CONFIG_FSL_DEBUG_SERVER
442 ram_top -= debug_server_get_dram_block_size();
445 /* Carve the MC private DRAM block from the end of DRAM */
446 #ifdef CONFIG_FSL_MC_ENET
447 ram_top -= mc_get_dram_block_size();
448 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);