2 * Copyright 2014-2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/errno.h>
10 #include <asm/system.h>
11 #include <asm/armv8/mmu.h>
13 #include <asm/arch/fsl_serdes.h>
14 #include <asm/arch/soc.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/speed.h>
18 #include <asm/arch/mp.h>
21 #include <fsl-mc/fsl_mc.h>
22 #ifdef CONFIG_FSL_ESDHC
23 #include <fsl_esdhc.h>
25 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
26 #include <asm/armv8/sec_firmware.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 struct mm_region *mem_map = early_map;
33 void cpu_name(char *name)
35 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
36 unsigned int i, svr, ver;
38 svr = gur_in32(&gur->svr);
39 ver = SVR_SOC_VER(svr);
41 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
42 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
43 strcpy(name, cpu_type_list[i].name);
45 if (IS_E_PROCESSOR(svr))
50 if (i == ARRAY_SIZE(cpu_type_list))
51 strcpy(name, "unknown");
54 #ifndef CONFIG_SYS_DCACHE_OFF
56 * To start MMU before DDR is available, we create MMU table in SRAM.
57 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
58 * levels of translation tables here to cover 40-bit address space.
59 * We use 4KB granule size, with 40 bits physical address, T0SZ=24
60 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
61 * Note, the debug print in cache_v8.c is not usable for debugging
62 * these early MMU tables because UART is not yet available.
64 static inline void early_mmu_setup(void)
66 unsigned int el = current_el();
68 /* global data is already setup, no allocation yet */
69 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
70 gd->arch.tlb_fillptr = gd->arch.tlb_addr;
71 gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
73 /* Create early page tables */
76 /* point TTBR to the new table */
77 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
78 get_tcr(el, NULL, NULL) &
79 ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
82 set_sctlr(get_sctlr() | CR_M);
86 * The final tables look similar to early tables, but different in detail.
87 * These tables are in DRAM. Sub tables are added to enable cache for
90 * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
91 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
93 static inline void final_mmu_setup(void)
95 u64 tlb_addr_save = gd->arch.tlb_addr;
96 unsigned int el = current_el();
97 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
103 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
104 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
107 * Only use gd->arch.secure_ram if the address is
108 * recalculated. Align to 4KB for MMU table.
110 /* put page tables in secure ram */
111 index = ARRAY_SIZE(final_map) - 2;
112 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
113 final_map[index].virt = gd->arch.secure_ram & ~0x3;
114 final_map[index].phys = final_map[index].virt;
115 final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
116 final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
117 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
118 tlb_addr_save = gd->arch.tlb_addr;
120 /* Use allocated (board_f.c) memory for TLB */
121 tlb_addr_save = gd->arch.tlb_allocated;
122 gd->arch.tlb_addr = tlb_addr_save;
127 /* Reset the fill ptr */
128 gd->arch.tlb_fillptr = tlb_addr_save;
130 /* Create normal system page tables */
133 /* Create emergency page tables */
134 gd->arch.tlb_addr = gd->arch.tlb_fillptr;
135 gd->arch.tlb_emerg = gd->arch.tlb_addr;
137 gd->arch.tlb_addr = tlb_addr_save;
139 /* flush new MMU table */
140 flush_dcache_range(gd->arch.tlb_addr,
141 gd->arch.tlb_addr + gd->arch.tlb_size);
143 /* point TTBR to the new table */
144 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
147 * EL3 MMU is already enabled, just need to invalidate TLB to load the
148 * new table. The new table is compatible with the current table, if
149 * MMU somehow walks through the new table before invalidation TLB,
150 * it still works. So we don't need to turn off MMU here.
151 * When EL2 MMU table is created by calling this function, MMU needs
154 set_sctlr(get_sctlr() | CR_M);
157 u64 get_page_table_size(void)
162 int arch_cpu_init(void)
165 __asm_invalidate_dcache_all();
166 __asm_invalidate_tlb_all();
168 set_sctlr(get_sctlr() | CR_C);
178 * This function is called from common/board_r.c.
179 * It recreates MMU table in main memory.
181 void enable_caches(void)
184 __asm_invalidate_tlb_all();
190 static inline u32 initiator_type(u32 cluster, int init_id)
192 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
193 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
196 type = gur_in32(&gur->tp_ityp[idx]);
197 if (type & TP_ITYP_AV)
205 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
206 int i = 0, count = 0;
207 u32 cluster, type, mask = 0;
212 cluster = gur_in32(&gur->tp_cluster[i].lower);
213 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
214 type = initiator_type(cluster, j);
216 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
222 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
228 * Return the number of cores on this SOC.
230 int cpu_numcores(void)
232 return hweight32(cpu_mask());
235 int fsl_qoriq_core_to_cluster(unsigned int core)
237 struct ccsr_gur __iomem *gur =
238 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
239 int i = 0, count = 0;
245 cluster = gur_in32(&gur->tp_cluster[i].lower);
246 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
247 if (initiator_type(cluster, j)) {
254 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
256 return -1; /* cannot identify the cluster */
259 u32 fsl_qoriq_core_to_type(unsigned int core)
261 struct ccsr_gur __iomem *gur =
262 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
263 int i = 0, count = 0;
269 cluster = gur_in32(&gur->tp_cluster[i].lower);
270 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
271 type = initiator_type(cluster, j);
279 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
281 return -1; /* cannot identify the cluster */
286 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
288 return gur_in32(&gur->svr);
291 #ifdef CONFIG_DISPLAY_CPUINFO
292 int print_cpuinfo(void)
294 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
295 struct sys_info sysinfo;
297 unsigned int i, core;
298 u32 type, rcw, svr = gur_in32(&gur->svr);
303 printf(" %s (0x%x)\n", buf, svr);
304 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
305 get_sys_info(&sysinfo);
306 puts("Clock Configuration:");
307 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
310 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
311 printf("CPU%d(%s):%-4s MHz ", core,
312 type == TY_ITYP_VER_A7 ? "A7 " :
313 (type == TY_ITYP_VER_A53 ? "A53" :
314 (type == TY_ITYP_VER_A57 ? "A57" :
315 (type == TY_ITYP_VER_A72 ? "A72" : " "))),
316 strmhz(buf, sysinfo.freq_processor[core]));
318 printf("\n Bus: %-4s MHz ",
319 strmhz(buf, sysinfo.freq_systembus));
320 printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
321 #ifdef CONFIG_SYS_DPAA_FMAN
322 printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
324 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
325 if (soc_has_dp_ddr()) {
326 printf(" DP-DDR: %-4s MT/s",
327 strmhz(buf, sysinfo.freq_ddrbus2));
333 * Display the RCW, so that no one gets confused as to what RCW
334 * we're actually using for this boot.
336 puts("Reset Configuration Word (RCW):");
337 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
338 rcw = gur_in32(&gur->rcwsr[i]);
340 printf("\n %08x:", i * 4);
341 printf(" %08x", rcw);
349 #ifdef CONFIG_FSL_ESDHC
350 int cpu_mmc_init(bd_t *bis)
352 return fsl_esdhc_mmc_init(bis);
356 int cpu_eth_init(bd_t *bis)
360 #ifdef CONFIG_FSL_MC_ENET
361 error = fsl_mc_ldpaa_init(bis);
363 #ifdef CONFIG_FMAN_ENET
364 fm_standard_init(bis);
369 int arch_early_init_r(void)
373 u32 psci_ver = 0xffffffff;
376 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
381 #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
382 /* Check the psci version to determine if the psci is supported */
383 psci_ver = sec_firmware_support_psci_version();
385 if (psci_ver == 0xffffffff) {
386 rv = fsl_layerscape_wake_seconday_cores();
388 printf("Did not wake secondary cores\n");
392 #ifdef CONFIG_SYS_HAS_SERDES
395 #ifdef CONFIG_FMAN_ENET
403 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
404 #ifdef CONFIG_FSL_LSCH3
405 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
407 #ifdef CONFIG_LS2080A
408 u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
410 #ifdef COUNTER_FREQUENCY_REAL
411 unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
413 /* Update with accurate clock frequency */
414 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
417 #ifdef CONFIG_FSL_LSCH3
418 /* Enable timebase for all clusters.
419 * It is safe to do so even some clusters are not enabled.
421 out_le32(cltbenr, 0xf);
424 #ifdef CONFIG_LS2080A
426 * In certain Layerscape SoCs, the clock for each core's
427 * has an enable bit in the PMU Physical Core Time Base Enable
428 * Register (PCTBENR), which allows the watchdog to operate.
430 setbits_le32(pctbenr, 0xff);
433 /* Enable clock for timer
434 * This is a global setting.
436 out_le32(cntcr, 0x1);
441 void reset_cpu(ulong addr)
443 u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
446 /* Raise RESET_REQ_B */
447 val = scfg_in32(rstcr);
449 scfg_out32(rstcr, val);
452 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
454 phys_size_t ram_top = ram_size;
456 #ifdef CONFIG_SYS_MEM_TOP_HIDE
457 #error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function
460 /* Carve the MC private DRAM block from the end of DRAM */
461 #ifdef CONFIG_FSL_MC_ENET
462 ram_top -= mc_get_dram_block_size();
463 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);