2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/compiler.h>
10 #include <asm/processor.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/soc.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
18 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
21 void get_sys_info(struct sys_info *sys_info)
23 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
25 struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
28 #if (defined(CONFIG_FSL_ESDHC) &&\
29 defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
30 defined(CONFIG_SYS_DPAA_FMAN)
34 struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
36 const u8 core_cplx_pll[8] = {
37 [0] = 0, /* CC1 PPL / 1 */
38 [1] = 0, /* CC1 PPL / 2 */
39 [4] = 1, /* CC2 PPL / 1 */
40 [5] = 1, /* CC2 PPL / 2 */
43 const u8 core_cplx_pll_div[8] = {
44 [0] = 1, /* CC1 PPL / 1 */
45 [1] = 2, /* CC1 PPL / 2 */
46 [4] = 1, /* CC2 PPL / 1 */
47 [5] = 2, /* CC2 PPL / 2 */
51 uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
52 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
53 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
55 sys_info->freq_systembus = sysclk;
56 #ifdef CONFIG_DDR_CLK_FREQ
57 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
59 sys_info->freq_ddrbus = sysclk;
63 sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
64 FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
65 FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
67 sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
68 FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
69 FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
70 sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
71 FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
72 FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
75 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
76 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
78 freq_c_pll[i] = sysclk * ratio[i];
80 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
83 for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) {
84 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
86 u32 cplx_pll = core_cplx_pll[c_pll_sel];
88 sys_info->freq_processor[cpu] =
89 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
93 sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
94 sys_info->freq_ddrbus *= 2;
97 #define HWA_CGA_M1_CLK_SEL 0xe0000000
98 #define HWA_CGA_M1_CLK_SHIFT 29
99 #ifdef CONFIG_SYS_DPAA_FMAN
100 rcw_tmp = in_be32(&gur->rcwsr[7]);
101 switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
103 sys_info->freq_fman[0] = freq_c_pll[0] / 2;
106 sys_info->freq_fman[0] = freq_c_pll[0] / 3;
109 sys_info->freq_fman[0] = freq_c_pll[1] / 2;
112 sys_info->freq_fman[0] = freq_c_pll[1] / 3;
115 printf("Error: Unknown FMan1 clock select!\n");
120 #define HWA_CGA_M2_CLK_SEL 0x00000007
121 #define HWA_CGA_M2_CLK_SHIFT 0
122 #ifdef CONFIG_FSL_ESDHC
123 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
124 rcw_tmp = in_be32(&gur->rcwsr[15]);
125 rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
126 sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
128 sys_info->freq_sdhc = sys_info->freq_systembus;
132 #if defined(CONFIG_FSL_IFC)
133 ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
134 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
136 sys_info->freq_localbus = sys_info->freq_systembus / ccr;
142 struct sys_info sys_info;
144 get_sys_info(&sys_info);
145 gd->cpu_clk = sys_info.freq_processor[0];
146 gd->bus_clk = sys_info.freq_systembus;
147 gd->mem_clk = sys_info.freq_ddrbus;
149 #ifdef CONFIG_FSL_ESDHC
150 gd->arch.sdhc_clk = sys_info.freq_sdhc;
153 if (gd->cpu_clk != 0)
159 ulong get_bus_freq(ulong dummy)
164 ulong get_ddr_freq(ulong dummy)
169 #ifdef CONFIG_FSL_ESDHC
170 int get_sdhc_freq(ulong dummy)
172 return gd->arch.sdhc_clk;
176 int get_serial_clock(void)
181 unsigned int mxc_get_clock(enum mxc_clock clk)
185 return get_bus_freq(0);
186 #if defined(CONFIG_FSL_ESDHC)
188 return get_sdhc_freq(0);
191 return get_bus_freq(0);
193 return get_bus_freq(0);
195 printf("Unsupported clock\n");