2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/compiler.h>
10 #include <asm/processor.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/soc.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
19 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
22 void get_sys_info(struct sys_info *sys_info)
24 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
26 struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
29 #if (defined(CONFIG_FSL_ESDHC) &&\
30 defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
31 defined(CONFIG_SYS_DPAA_FMAN)
35 struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
37 const u8 core_cplx_pll[8] = {
38 [0] = 0, /* CC1 PPL / 1 */
39 [1] = 0, /* CC1 PPL / 2 */
40 [4] = 1, /* CC2 PPL / 1 */
41 [5] = 1, /* CC2 PPL / 2 */
44 const u8 core_cplx_pll_div[8] = {
45 [0] = 1, /* CC1 PPL / 1 */
46 [1] = 2, /* CC1 PPL / 2 */
47 [4] = 1, /* CC2 PPL / 1 */
48 [5] = 2, /* CC2 PPL / 2 */
52 uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
53 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
54 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
55 unsigned long cluster_clk;
57 sys_info->freq_systembus = sysclk;
58 #ifndef CONFIG_CLUSTER_CLK_FREQ
59 #define CONFIG_CLUSTER_CLK_FREQ CONFIG_SYS_CLK_FREQ
61 cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
63 #ifdef CONFIG_DDR_CLK_FREQ
64 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
66 sys_info->freq_ddrbus = sysclk;
69 /* The freq_systembus is used to record frequency of platform PLL */
70 sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
71 FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
72 FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
74 #ifdef CONFIG_ARCH_LS1012A
75 sys_info->freq_ddrbus = 2 * sys_info->freq_systembus;
77 sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
78 FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
79 FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
82 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
83 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
85 freq_c_pll[i] = cluster_clk * ratio[i];
87 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
90 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
91 cluster = fsl_qoriq_core_to_cluster(cpu);
92 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
94 u32 cplx_pll = core_cplx_pll[c_pll_sel];
96 sys_info->freq_processor[cpu] =
97 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
100 #define HWA_CGA_M1_CLK_SEL 0xe0000000
101 #define HWA_CGA_M1_CLK_SHIFT 29
102 #ifdef CONFIG_SYS_DPAA_FMAN
103 rcw_tmp = in_be32(&gur->rcwsr[7]);
104 switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
106 sys_info->freq_fman[0] = freq_c_pll[0] / 2;
109 sys_info->freq_fman[0] = freq_c_pll[0] / 3;
112 sys_info->freq_fman[0] = freq_c_pll[0] / 4;
115 sys_info->freq_fman[0] = sys_info->freq_systembus;
118 sys_info->freq_fman[0] = freq_c_pll[1] / 2;
121 sys_info->freq_fman[0] = freq_c_pll[1] / 3;
124 printf("Error: Unknown FMan1 clock select!\n");
129 #define HWA_CGA_M2_CLK_SEL 0x00000007
130 #define HWA_CGA_M2_CLK_SHIFT 0
131 #ifdef CONFIG_FSL_ESDHC
132 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
133 rcw_tmp = in_be32(&gur->rcwsr[15]);
134 switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
136 sys_info->freq_sdhc = freq_c_pll[1];
139 sys_info->freq_sdhc = freq_c_pll[1] / 2;
142 sys_info->freq_sdhc = freq_c_pll[1] / 3;
145 sys_info->freq_sdhc = freq_c_pll[0] / 2;
148 printf("Error: Unknown ESDHC clock select!\n");
152 sys_info->freq_sdhc = (sys_info->freq_systembus /
153 CONFIG_SYS_FSL_PCLK_DIV) /
154 CONFIG_SYS_FSL_SDHC_CLK_DIV;
158 #if defined(CONFIG_FSL_IFC)
159 ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
160 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
162 sys_info->freq_localbus = sys_info->freq_systembus / ccr;
168 struct sys_info sys_info;
170 get_sys_info(&sys_info);
171 gd->cpu_clk = sys_info.freq_processor[0];
172 gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
173 gd->mem_clk = sys_info.freq_ddrbus;
175 #ifdef CONFIG_FSL_ESDHC
176 gd->arch.sdhc_clk = sys_info.freq_sdhc;
179 if (gd->cpu_clk != 0)
185 /********************************************
187 * return platform clock in Hz
188 *********************************************/
189 ulong get_bus_freq(ulong dummy)
197 ulong get_ddr_freq(ulong dummy)
205 #ifdef CONFIG_FSL_ESDHC
206 int get_sdhc_freq(ulong dummy)
208 if (!gd->arch.sdhc_clk)
211 return gd->arch.sdhc_clk;
215 int get_serial_clock(void)
217 return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
220 int get_i2c_freq(ulong dummy)
222 return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
225 int get_dspi_freq(ulong dummy)
227 return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
230 #ifdef CONFIG_FSL_LPUART
231 int get_uart_freq(ulong dummy)
233 return get_bus_freq(0) / CONFIG_SYS_FSL_LPUART_CLK_DIV;
237 unsigned int mxc_get_clock(enum mxc_clock clk)
241 return get_i2c_freq(0);
242 #if defined(CONFIG_FSL_ESDHC)
244 return get_sdhc_freq(0);
247 return get_dspi_freq(0);
248 #ifdef CONFIG_FSL_LPUART
250 return get_uart_freq(0);
253 printf("Unsupported clock\n");