2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/compiler.h>
10 #include <asm/processor.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/soc.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
19 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
22 void get_sys_info(struct sys_info *sys_info)
24 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
25 #if (defined(CONFIG_FSL_ESDHC) &&\
26 defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
27 defined(CONFIG_SYS_DPAA_FMAN)
31 struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
33 const u8 core_cplx_pll[8] = {
34 [0] = 0, /* CC1 PPL / 1 */
35 [1] = 0, /* CC1 PPL / 2 */
36 [4] = 1, /* CC2 PPL / 1 */
37 [5] = 1, /* CC2 PPL / 2 */
40 const u8 core_cplx_pll_div[8] = {
41 [0] = 1, /* CC1 PPL / 1 */
42 [1] = 2, /* CC1 PPL / 2 */
43 [4] = 1, /* CC2 PPL / 1 */
44 [5] = 2, /* CC2 PPL / 2 */
48 uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
49 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
50 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
51 unsigned long cluster_clk;
53 sys_info->freq_systembus = sysclk;
54 #ifndef CONFIG_CLUSTER_CLK_FREQ
55 #define CONFIG_CLUSTER_CLK_FREQ CONFIG_SYS_CLK_FREQ
57 cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
59 #ifdef CONFIG_DDR_CLK_FREQ
60 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
62 sys_info->freq_ddrbus = sysclk;
65 /* The freq_systembus is used to record frequency of platform PLL */
66 sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
67 FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
68 FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
70 #ifdef CONFIG_ARCH_LS1012A
71 sys_info->freq_ddrbus = 2 * sys_info->freq_systembus;
73 sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
74 FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
75 FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
78 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
79 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
81 freq_c_pll[i] = cluster_clk * ratio[i];
83 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
86 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
87 cluster = fsl_qoriq_core_to_cluster(cpu);
88 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
90 u32 cplx_pll = core_cplx_pll[c_pll_sel];
92 sys_info->freq_processor[cpu] =
93 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
96 #define HWA_CGA_M1_CLK_SEL 0xe0000000
97 #define HWA_CGA_M1_CLK_SHIFT 29
98 #ifdef CONFIG_SYS_DPAA_FMAN
99 rcw_tmp = in_be32(&gur->rcwsr[7]);
100 switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
102 sys_info->freq_fman[0] = freq_c_pll[0] / 2;
105 sys_info->freq_fman[0] = freq_c_pll[0] / 3;
108 sys_info->freq_fman[0] = freq_c_pll[0] / 4;
111 sys_info->freq_fman[0] = sys_info->freq_systembus;
114 sys_info->freq_fman[0] = freq_c_pll[1] / 2;
117 sys_info->freq_fman[0] = freq_c_pll[1] / 3;
120 printf("Error: Unknown FMan1 clock select!\n");
125 #define HWA_CGA_M2_CLK_SEL 0x00000007
126 #define HWA_CGA_M2_CLK_SHIFT 0
127 #ifdef CONFIG_FSL_ESDHC
128 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
129 rcw_tmp = in_be32(&gur->rcwsr[15]);
130 switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
132 sys_info->freq_sdhc = freq_c_pll[1];
135 sys_info->freq_sdhc = freq_c_pll[1] / 2;
138 sys_info->freq_sdhc = freq_c_pll[1] / 3;
141 sys_info->freq_sdhc = freq_c_pll[0] / 2;
144 printf("Error: Unknown ESDHC clock select!\n");
148 sys_info->freq_sdhc = (sys_info->freq_systembus /
149 CONFIG_SYS_FSL_PCLK_DIV) /
150 CONFIG_SYS_FSL_SDHC_CLK_DIV;
154 #if defined(CONFIG_FSL_IFC)
155 sys_info->freq_localbus = sys_info->freq_systembus /
156 CONFIG_SYS_FSL_IFC_CLK_DIV;
162 struct sys_info sys_info;
164 get_sys_info(&sys_info);
165 gd->cpu_clk = sys_info.freq_processor[0];
166 gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
167 gd->mem_clk = sys_info.freq_ddrbus;
169 #ifdef CONFIG_FSL_ESDHC
170 gd->arch.sdhc_clk = sys_info.freq_sdhc;
173 if (gd->cpu_clk != 0)
179 /********************************************
181 * return platform clock in Hz
182 *********************************************/
183 ulong get_bus_freq(ulong dummy)
191 ulong get_ddr_freq(ulong dummy)
199 #ifdef CONFIG_FSL_ESDHC
200 int get_sdhc_freq(ulong dummy)
202 if (!gd->arch.sdhc_clk)
205 return gd->arch.sdhc_clk;
209 int get_serial_clock(void)
211 return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
214 int get_i2c_freq(ulong dummy)
216 return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
219 int get_dspi_freq(ulong dummy)
221 return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
224 #ifdef CONFIG_FSL_LPUART
225 int get_uart_freq(ulong dummy)
227 return get_bus_freq(0) / CONFIG_SYS_FSL_LPUART_CLK_DIV;
231 unsigned int mxc_get_clock(enum mxc_clock clk)
235 return get_i2c_freq(0);
236 #if defined(CONFIG_FSL_ESDHC)
238 return get_sdhc_freq(0);
241 return get_dspi_freq(0);
242 #ifdef CONFIG_FSL_LPUART
244 return get_uart_freq(0);
247 printf("Unsupported clock\n");