2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/compiler.h>
10 #include <asm/processor.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/soc.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
19 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
22 void get_sys_info(struct sys_info *sys_info)
24 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
26 struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
29 #if (defined(CONFIG_FSL_ESDHC) &&\
30 defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
31 defined(CONFIG_SYS_DPAA_FMAN)
35 struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
37 const u8 core_cplx_pll[8] = {
38 [0] = 0, /* CC1 PPL / 1 */
39 [1] = 0, /* CC1 PPL / 2 */
40 [4] = 1, /* CC2 PPL / 1 */
41 [5] = 1, /* CC2 PPL / 2 */
44 const u8 core_cplx_pll_div[8] = {
45 [0] = 1, /* CC1 PPL / 1 */
46 [1] = 2, /* CC1 PPL / 2 */
47 [4] = 1, /* CC2 PPL / 1 */
48 [5] = 2, /* CC2 PPL / 2 */
52 uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
53 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
54 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
56 sys_info->freq_systembus = sysclk;
57 #ifdef CONFIG_DDR_CLK_FREQ
58 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
60 sys_info->freq_ddrbus = sysclk;
64 sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
65 FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
66 FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
68 sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
69 FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
70 FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
71 sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
72 FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
73 FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
76 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
77 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
79 freq_c_pll[i] = sysclk * ratio[i];
81 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
84 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
85 cluster = fsl_qoriq_core_to_cluster(cpu);
86 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
88 u32 cplx_pll = core_cplx_pll[c_pll_sel];
90 sys_info->freq_processor[cpu] =
91 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
95 sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
96 sys_info->freq_ddrbus *= 2;
99 #define HWA_CGA_M1_CLK_SEL 0xe0000000
100 #define HWA_CGA_M1_CLK_SHIFT 29
101 #ifdef CONFIG_SYS_DPAA_FMAN
102 rcw_tmp = in_be32(&gur->rcwsr[7]);
103 switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
105 sys_info->freq_fman[0] = freq_c_pll[0] / 2;
108 sys_info->freq_fman[0] = freq_c_pll[0] / 3;
111 sys_info->freq_fman[0] = freq_c_pll[1] / 2;
114 sys_info->freq_fman[0] = freq_c_pll[1] / 3;
117 printf("Error: Unknown FMan1 clock select!\n");
122 #define HWA_CGA_M2_CLK_SEL 0x00000007
123 #define HWA_CGA_M2_CLK_SHIFT 0
124 #ifdef CONFIG_FSL_ESDHC
125 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
126 rcw_tmp = in_be32(&gur->rcwsr[15]);
127 rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
128 sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
130 sys_info->freq_sdhc = sys_info->freq_systembus;
134 #if defined(CONFIG_FSL_IFC)
135 ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
136 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
138 sys_info->freq_localbus = sys_info->freq_systembus / ccr;
144 struct sys_info sys_info;
146 get_sys_info(&sys_info);
147 gd->cpu_clk = sys_info.freq_processor[0];
148 gd->bus_clk = sys_info.freq_systembus;
149 gd->mem_clk = sys_info.freq_ddrbus;
151 #ifdef CONFIG_FSL_ESDHC
152 gd->arch.sdhc_clk = sys_info.freq_sdhc;
155 if (gd->cpu_clk != 0)
161 ulong get_bus_freq(ulong dummy)
166 ulong get_ddr_freq(ulong dummy)
171 #ifdef CONFIG_FSL_ESDHC
172 int get_sdhc_freq(ulong dummy)
174 return gd->arch.sdhc_clk;
178 int get_serial_clock(void)
183 unsigned int mxc_get_clock(enum mxc_clock clk)
187 return get_bus_freq(0);
188 #if defined(CONFIG_FSL_ESDHC)
190 return get_sdhc_freq(0);
193 return get_bus_freq(0);
195 return get_bus_freq(0);
197 printf("Unsupported clock\n");