git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c

   1 /*
   2  * Copyright 2014-2015, Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  * Derived from arch/power/cpu/mpc85xx/speed.c
   7  */
   8
   9 #include <common.h>
  10 #include <linux/compiler.h>
  11 #include <fsl_ifc.h>
  12 #include <asm/processor.h>
  13 #include <asm/io.h>
  14 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/soc.h>
  17 #include "cpu.h"
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
  22 #define CONFIG_SYS_FSL_NUM_CC_PLLS      6
  23 #endif
  24
  25
  26 void get_sys_info(struct sys_info *sys_info)
  27 {
  28         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  29 #ifdef CONFIG_FSL_IFC
  30         struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
  31         u32 ccr;
  32 #endif
  33         struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
  34                 (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR),
  35                 (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR)
  36         };
  37         struct ccsr_clk_ctrl __iomem *clk_ctrl =
  38                 (void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR);
  39         unsigned int cpu;
  40         const u8 core_cplx_pll[16] = {
  41                 [0] = 0,        /* CC1 PPL / 1 */
  42                 [1] = 0,        /* CC1 PPL / 2 */
  43                 [2] = 0,        /* CC1 PPL / 4 */
  44                 [4] = 1,        /* CC2 PPL / 1 */
  45                 [5] = 1,        /* CC2 PPL / 2 */
  46                 [6] = 1,        /* CC2 PPL / 4 */
  47                 [8] = 2,        /* CC3 PPL / 1 */
  48                 [9] = 2,        /* CC3 PPL / 2 */
  49                 [10] = 2,       /* CC3 PPL / 4 */
  50                 [12] = 3,       /* CC4 PPL / 1 */
  51                 [13] = 3,       /* CC4 PPL / 2 */
  52                 [14] = 3,       /* CC4 PPL / 4 */
  53         };
  54
  55         const u8 core_cplx_pll_div[16] = {
  56                 [0] = 1,        /* CC1 PPL / 1 */
  57                 [1] = 2,        /* CC1 PPL / 2 */
  58                 [2] = 4,        /* CC1 PPL / 4 */
  59                 [4] = 1,        /* CC2 PPL / 1 */
  60                 [5] = 2,        /* CC2 PPL / 2 */
  61                 [6] = 4,        /* CC2 PPL / 4 */
  62                 [8] = 1,        /* CC3 PPL / 1 */
  63                 [9] = 2,        /* CC3 PPL / 2 */
  64                 [10] = 4,       /* CC3 PPL / 4 */
  65                 [12] = 1,       /* CC4 PPL / 1 */
  66                 [13] = 2,       /* CC4 PPL / 2 */
  67                 [14] = 4,       /* CC4 PPL / 4 */
  68         };
  69
  70         uint i, cluster;
  71         uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
  72         uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
  73         unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
  74         int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
  75         u32 c_pll_sel, cplx_pll;
  76         void *offset;
  77
  78         sys_info->freq_systembus = sysclk;
  79 #ifdef CONFIG_DDR_CLK_FREQ
  80         sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
  81 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  82         sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
  83 #endif
  84 #else
  85         sys_info->freq_ddrbus = sysclk;
  86 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  87         sys_info->freq_ddrbus2 = sysclk;
  88 #endif
  89 #endif
  90
  91         sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
  92                         FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
  93                         FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
  94         /* Platform clock is half of platform PLL */
  95         sys_info->freq_systembus /= 2;
  96         sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
  97                         FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
  98                         FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
  99 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 100         sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
 101                         FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
 102                         FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
 103 #endif
 104
 105         for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
 106                 /*
 107                  * fixme: prefer to combine the following into one line, but
 108                  * cannot pass compiling without warning about in_le32.
 109                  */
 110                 offset = (void *)((size_t)clk_grp[i/3] +
 111                          offsetof(struct ccsr_clk_cluster_group,
 112                                   pllngsr[i%3].gsr));
 113                 ratio[i] = (in_le32(offset) >> 1) & 0x3f;
 114                 freq_c_pll[i] = sysclk * ratio[i];
 115         }
 116
 117         for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
 118                 cluster = fsl_qoriq_core_to_cluster(cpu);
 119                 c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27)
 120                             & 0xf;
 121                 cplx_pll = core_cplx_pll[c_pll_sel];
 122                 cplx_pll += cc_group[cluster] - 1;
 123                 sys_info->freq_processor[cpu] =
 124                         freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 125         }
 126
 127 #if defined(CONFIG_FSL_IFC)
 128         ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
 129         ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
 130
 131         sys_info->freq_localbus = sys_info->freq_systembus / ccr;
 132 #endif
 133 }
 134
 135
 136 int get_clocks(void)
 137 {
 138         struct sys_info sys_info;
 139         get_sys_info(&sys_info);
 140         gd->cpu_clk = sys_info.freq_processor[0];
 141         gd->bus_clk = sys_info.freq_systembus;
 142         gd->mem_clk = sys_info.freq_ddrbus;
 143 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 144         gd->arch.mem2_clk = sys_info.freq_ddrbus2;
 145 #endif
 146 #if defined(CONFIG_FSL_ESDHC)
 147         gd->arch.sdhc_clk = gd->bus_clk / 2;
 148 #endif /* defined(CONFIG_FSL_ESDHC) */
 149
 150         if (gd->cpu_clk != 0)
 151                 return 0;
 152         else
 153                 return 1;
 154 }
 155
 156 /********************************************
 157  * get_bus_freq
 158  * return system bus freq in Hz
 159  *********************************************/
 160 ulong get_bus_freq(ulong dummy)
 161 {
 162         if (!gd->bus_clk)
 163                 get_clocks();
 164
 165         return gd->bus_clk;
 166 }
 167
 168 /********************************************
 169  * get_ddr_freq
 170  * return ddr bus freq in Hz
 171  *********************************************/
 172 ulong get_ddr_freq(ulong ctrl_num)
 173 {
 174         if (!gd->mem_clk)
 175                 get_clocks();
 176
 177         /*
 178          * DDR controller 0 & 1 are on memory complex 0
 179          * DDR controler 2 is on memory complext 1
 180          */
 181 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 182         if (ctrl_num >= 2)
 183                 return gd->arch.mem2_clk;
 184 #endif
 185
 186         return gd->mem_clk;
 187 }
 188
 189 unsigned int mxc_get_clock(enum mxc_clock clk)
 190 {
 191         switch (clk) {
 192         case MXC_I2C_CLK:
 193                 return get_bus_freq(0) / 2;
 194         case MXC_DSPI_CLK:
 195                 return get_bus_freq(0) / 2;
 196         default:
 197                 printf("Unsupported clock\n");
 198         }
 199         return 0;
 200 }