2 * Copyright 2014-2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/soc.h>
15 #include <asm/global_data.h>
16 #include <asm/arch-fsl-layerscape/config.h>
17 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
20 #ifdef CONFIG_SYS_FSL_DDR
21 #include <fsl_ddr_sdram.h>
24 #ifdef CONFIG_CHAIN_OF_TRUST
25 #include <fsl_validate.h>
27 #include <fsl_immap.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 bool soc_has_dp_ddr(void)
33 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
34 u32 svr = gur_in32(&gur->svr);
36 /* LS2085A, LS2088A, LS2048A has DP_DDR */
37 if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
38 (SVR_SOC_VER(svr) == SVR_LS2088A) ||
39 (SVR_SOC_VER(svr) == SVR_LS2048A))
45 bool soc_has_aiop(void)
47 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
48 u32 svr = gur_in32(&gur->svr);
50 /* LS2085A has AIOP */
51 if (SVR_SOC_VER(svr) == SVR_LS2085A)
57 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
59 scfg_clrsetbits32(scfg + offset / 4,
61 SCFG_USB_TXVREFTUNE << 6);
64 static void erratum_a009008(void)
66 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
67 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
69 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
70 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
71 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
72 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
73 #elif defined(CONFIG_ARCH_LS2080A)
74 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
76 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
79 static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
81 scfg_clrbits32(scfg + offset / 4,
82 SCFG_USB_SQRXTUNE_MASK << 23);
85 static void erratum_a009798(void)
87 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
88 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
90 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
91 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
92 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
93 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
94 #elif defined(CONFIG_ARCH_LS2080A)
95 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
97 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
100 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
101 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
103 scfg_clrsetbits32(scfg + offset / 4,
105 SCFG_USB_PCSTXSWINGFULL << 9);
109 static void erratum_a008997(void)
111 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
112 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
113 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
115 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
116 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
117 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
119 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
122 #if defined(CONFIG_FSL_LSCH3)
124 * This erratum requires setting a value to eddrtqcr1 to
125 * optimal the DDR performance.
127 static void erratum_a008336(void)
129 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
132 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
133 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
134 if (fsl_ddr_get_version(0) == 0x50200)
135 out_le32(eddrtqcr1, 0x63b30002);
137 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
138 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
139 if (fsl_ddr_get_version(0) == 0x50200)
140 out_le32(eddrtqcr1, 0x63b30002);
146 * This erratum requires a register write before being Memory
147 * controller 3 being enabled.
149 static void erratum_a008514(void)
151 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
154 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
155 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
156 out_le32(eddrtqcr1, 0x63b20002);
160 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
161 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
163 static unsigned long get_internval_val_mhz(void)
165 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
167 * interval is the number of platform cycles(MHz) between
168 * wake up events generated by EPU.
170 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
173 interval_mhz = simple_strtoul(interval, NULL, 10);
178 void erratum_a009635(void)
181 unsigned long interval_mhz = get_internval_val_mhz();
186 val = in_le32(DCSR_CGACRE5);
187 writel(val | 0x00000200, DCSR_CGACRE5);
189 val = in_le32(EPU_EPCMPR5);
190 writel(interval_mhz, EPU_EPCMPR5);
191 val = in_le32(EPU_EPCCR5);
192 writel(val | 0x82820000, EPU_EPCCR5);
193 val = in_le32(EPU_EPSMCR5);
194 writel(val | 0x002f0000, EPU_EPSMCR5);
195 val = in_le32(EPU_EPECR5);
196 writel(val | 0x20000000, EPU_EPECR5);
197 val = in_le32(EPU_EPGCR);
198 writel(val | 0x80000000, EPU_EPGCR);
200 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
202 static void erratum_rcw_src(void)
204 #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
205 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
206 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
209 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
210 val &= ~DCFG_PORSR1_RCW_SRC;
211 val |= DCFG_PORSR1_RCW_SRC_NOR;
212 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
216 #define I2C_DEBUG_REG 0x6
217 #define I2C_GLITCH_EN 0x8
219 * This erratum requires setting glitch_en bit to enable
220 * digital glitch filter to improve clock stability.
222 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
223 static void erratum_a009203(void)
226 #ifdef CONFIG_SYS_I2C
227 #ifdef I2C1_BASE_ADDR
228 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
230 writeb(I2C_GLITCH_EN, ptr);
232 #ifdef I2C2_BASE_ADDR
233 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
235 writeb(I2C_GLITCH_EN, ptr);
237 #ifdef I2C3_BASE_ADDR
238 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
240 writeb(I2C_GLITCH_EN, ptr);
242 #ifdef I2C4_BASE_ADDR
243 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
245 writeb(I2C_GLITCH_EN, ptr);
251 void bypass_smmu(void)
254 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
255 out_le32(SMMU_SCR0, val);
256 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
257 out_le32(SMMU_NSCR0, val);
259 void fsl_lsch3_early_init_f(void)
262 init_early_memctl_regs(); /* tighten IFC timing */
263 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
271 #ifdef CONFIG_CHAIN_OF_TRUST
272 /* In case of Secure Boot, the IBR configures the SMMU
273 * to allow only Secure transactions.
274 * SMMU must be reset in bypass mode.
275 * Set the ClientPD bit and Clear the USFCFG Bit
277 if (fsl_check_boot_mode_secure() == 1)
282 #ifdef CONFIG_SCSI_AHCI_PLAT
285 struct ccsr_ahci __iomem *ccsr_ahci;
287 ccsr_ahci = (void *)CONFIG_SYS_SATA2;
288 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
289 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
290 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
292 ccsr_ahci = (void *)CONFIG_SYS_SATA1;
293 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
294 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
295 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
297 ahci_init((void __iomem *)CONFIG_SYS_SATA1);
304 #elif defined(CONFIG_FSL_LSCH2)
305 #ifdef CONFIG_SCSI_AHCI_PLAT
308 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
310 /* Disable SATA ECC */
311 out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
312 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
313 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
314 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
316 ahci_init((void __iomem *)CONFIG_SYS_SATA);
323 static void erratum_a009929(void)
325 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
326 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
327 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
328 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
330 rstrqmr1 |= 0x00000400;
331 gur_out32(&gur->rstrqmr1, rstrqmr1);
332 writel(0x01000000, dcsr_cop_ccp);
337 * This erratum requires setting a value to eddrtqcr1 to optimal
338 * the DDR performance. The eddrtqcr1 register is in SCFG space
339 * of LS1043A and the offset is 0x157_020c.
341 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
342 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
343 #error A009660 and A008514 can not be both enabled.
346 static void erratum_a009660(void)
348 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
349 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
350 out_be32(eddrtqcr1, 0x63b20042);
354 static void erratum_a008850_early(void)
356 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
358 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
359 CONFIG_SYS_CCI400_OFFSET);
360 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
362 /* Skip if running at lower exception level */
363 if (current_el() < 3)
366 /* disables propagation of barrier transactions to DDRC from CCI400 */
367 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
369 /* disable the re-ordering in DDRC */
370 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
374 void erratum_a008850_post(void)
376 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
378 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
379 CONFIG_SYS_CCI400_OFFSET);
380 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
383 /* Skip if running at lower exception level */
384 if (current_el() < 3)
387 /* enable propagation of barrier transactions to DDRC from CCI400 */
388 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
390 /* enable the re-ordering in DDRC */
391 tmp = ddr_in32(&ddr->eor);
392 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
393 ddr_out32(&ddr->eor, tmp);
397 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
398 void erratum_a010315(void)
402 for (i = PCIE1; i <= PCIE4; i++)
403 if (!is_serdes_configured(i)) {
404 debug("PCIe%d: disabled all R/W permission!\n", i);
405 set_pcie_ns_access(i, 0);
410 static void erratum_a010539(void)
412 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
413 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
416 porsr1 = in_be32(&gur->porsr1);
417 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
418 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
423 /* Get VDD in the unit mV from voltage ID */
424 int get_core_volt_from_fuse(void)
426 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
431 fusesr = in_be32(&gur->dcfg_fusesr);
432 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
433 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
434 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
435 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
436 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
437 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
439 debug("%s: VID = 0x%x\n", __func__, vid);
441 case 0x00: /* VID isn't supported */
443 debug("%s: The VID feature is not supported\n", __func__);
445 case 0x08: /* 0.9V silicon */
448 case 0x10: /* 1.0V silicon */
451 default: /* Other core voltage */
453 printf("%s: The VID(%x) isn't supported\n", __func__, vid);
456 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
461 __weak int board_switch_core_volt(u32 vdd)
466 static int setup_core_volt(u32 vdd)
468 return board_setup_core_volt(vdd);
471 #ifdef CONFIG_SYS_FSL_DDR
472 static void ddr_enable_0v9_volt(bool en)
474 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
477 tmp = ddr_in32(&ddr->ddr_cdr1);
480 tmp |= DDR_CDR1_V0PT9_EN;
482 tmp &= ~DDR_CDR1_V0PT9_EN;
484 ddr_out32(&ddr->ddr_cdr1, tmp);
488 int setup_chip_volt(void)
492 vdd = get_core_volt_from_fuse();
493 /* Nothing to do for silicons doesn't support VID */
497 if (setup_core_volt(vdd))
498 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
499 #ifdef CONFIG_SYS_HAS_SERDES
500 if (setup_serdes_volt(vdd))
501 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
504 #ifdef CONFIG_SYS_FSL_DDR
506 ddr_enable_0v9_volt(true);
512 void fsl_lsch2_early_init_f(void)
514 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
515 CONFIG_SYS_CCI400_OFFSET);
516 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
518 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
519 enable_layerscape_ns_access();
522 #ifdef CONFIG_FSL_IFC
523 init_early_memctl_regs(); /* tighten IFC timing */
526 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
527 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
529 /* Make SEC reads and writes snoopable */
530 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
531 SCFG_SNPCNFGCR_SECWRSNP |
532 SCFG_SNPCNFGCR_SATARDSNP |
533 SCFG_SNPCNFGCR_SATAWRSNP);
536 * Enable snoop requests and DVM message requests for
537 * Slave insterface S4 (A53 core cluster)
539 if (current_el() == 3) {
540 out_le32(&cci->slave[4].snoop_ctrl,
541 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
545 erratum_a008850_early(); /* part 1 of 2 */
555 #ifdef CONFIG_QSPI_AHB_INIT
556 /* Enable 4bytes address support and fast read */
557 int qspi_ahb_init(void)
559 u32 *qspi_lut, lut_key, *qspi_key;
561 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
562 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
564 lut_key = in_be32(qspi_key);
566 if (lut_key == 0x5af05af0) {
567 /* That means the register is BE */
568 out_be32(qspi_key, 0x5af05af0);
569 /* Unlock the lut table */
570 out_be32(qspi_key + 1, 0x00000002);
571 out_be32(qspi_lut, 0x0820040c);
572 out_be32(qspi_lut + 1, 0x1c080c08);
573 out_be32(qspi_lut + 2, 0x00002400);
574 /* Lock the lut table */
575 out_be32(qspi_key, 0x5af05af0);
576 out_be32(qspi_key + 1, 0x00000001);
578 /* That means the register is LE */
579 out_le32(qspi_key, 0x5af05af0);
580 /* Unlock the lut table */
581 out_le32(qspi_key + 1, 0x00000002);
582 out_le32(qspi_lut, 0x0820040c);
583 out_le32(qspi_lut + 1, 0x1c080c08);
584 out_le32(qspi_lut + 2, 0x00002400);
585 /* Lock the lut table */
586 out_le32(qspi_key, 0x5af05af0);
587 out_le32(qspi_key + 1, 0x00000001);
594 #ifdef CONFIG_BOARD_LATE_INIT
595 int board_late_init(void)
597 #ifdef CONFIG_SCSI_AHCI_PLAT
600 #ifdef CONFIG_CHAIN_OF_TRUST
601 fsl_setenv_chain_of_trust();
603 #ifdef CONFIG_QSPI_AHB_INIT