1 /* vi: set ts=8 sw=8 noet: */
3 * u-boot - Startup Code for XScale IXP
5 * Copyright (C) 2003 Kyle Harris <kharris@nexus-tech.net>
7 * Based on startup code example contained in the
8 * Intel IXP4xx Programmer's Guide and past u-boot Start.S
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm-offsets.h>
33 #include <asm/arch/ixp425.h>
35 #define MMU_Control_M 0x001 /* Enable MMU */
36 #define MMU_Control_A 0x002 /* Enable address alignment faults */
37 #define MMU_Control_C 0x004 /* Enable cache */
38 #define MMU_Control_W 0x008 /* Enable write-buffer */
39 #define MMU_Control_P 0x010 /* Compatability: 32 bit code */
40 #define MMU_Control_D 0x020 /* Compatability: 32 bit data */
41 #define MMU_Control_L 0x040 /* Compatability: */
42 #define MMU_Control_B 0x080 /* Enable Big-Endian */
43 #define MMU_Control_S 0x100 /* Enable system protection */
44 #define MMU_Control_R 0x200 /* Enable ROM protection */
45 #define MMU_Control_I 0x1000 /* Enable Instruction cache */
46 #define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */
47 #define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
54 .macro DELAY_FOR cycles, reg0
60 /* wait for coprocessor write complete */
62 mrc p15,0,\reg,c2,c0,0
69 ldr pc, _undefined_instruction
70 ldr pc, _software_interrupt
71 ldr pc, _prefetch_abort
77 _undefined_instruction: .word undefined_instruction
78 _software_interrupt: .word software_interrupt
79 _prefetch_abort: .word prefetch_abort
80 _data_abort: .word data_abort
81 _not_used: .word not_used
85 .balignl 16,0xdeadbeef
89 * Startup Code (reset vector)
91 * do important init only if we don't start from memory!
92 * - relocate armboot to ram
94 * - jump to second stage
99 .word CONFIG_SYS_TEXT_BASE
102 * These are defined in the board-specific linker script.
112 #ifdef CONFIG_USE_IRQ
113 /* IRQ stack memory (calculated at run-time) */
114 .globl IRQ_STACK_START
118 /* IRQ stack memory (calculated at run-time) */
119 .globl FIQ_STACK_START
124 /* IRQ stack memory (calculated at run-time) + 8 bytes */
125 .globl IRQ_STACK_START_IN
129 .globl _datarel_start
131 .word __datarel_start
133 .globl _datarelrolocal_start
134 _datarelrolocal_start:
135 .word __datarelrolocal_start
137 .globl _datarellocal_start
139 .word __datarellocal_start
141 .globl _datarelro_start
143 .word __datarelro_start
154 * the actual reset code
158 /* disable mmu, set big-endian */
160 mcr p15, 0, r0, c1, c0, 0
163 /* invalidate I & D caches & BTB */
164 mcr p15, 0, r0, c7, c7, 0
167 /* invalidate I & Data TLB */
168 mcr p15, 0, r0, c8, c7, 0
171 /* drain write and fill buffers */
172 mcr p15, 0, r0, c7, c10, 4
175 /* disable write buffer coalescing */
176 mrc p15, 0, r0, c1, c0, 1
178 mcr p15, 0, r0, c1, c0, 1
181 /* set EXP CS0 to the optimum timing */
182 ldr r1, =CONFIG_SYS_EXP_CS0
183 ldr r2, =IXP425_EXP_CS0
186 /* make sure flash is visible at 0 */
188 ldr r2, =IXP425_EXP_CFG0
190 orr r1, r1, #0x80000000
193 mov r1, #CONFIG_SYS_SDR_CONFIG
194 ldr r2, =IXP425_SDR_CONFIG
197 /* disable refresh cycles */
199 ldr r3, =IXP425_SDR_REFRESH
202 /* send nop command */
204 ldr r4, =IXP425_SDR_IR
208 /* set SDRAM internal refresh val */
209 ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
213 /* send precharge-all command to close all open banks */
218 /* provide 8 auto-refresh cycles */
226 /* set mode register in sdram */
227 mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
231 /* send normal operation command */
239 add r2, r0, #CONFIG_SYS_MONITOR_LEN
249 /* invalidate I & D caches & BTB */
250 mcr p15, 0, r0, c7, c7, 0
253 /* invalidate I & Data TLB */
254 mcr p15, 0, r0, c8, c7, 0
257 /* drain write and fill buffers */
258 mcr p15, 0, r0, c7, c10, 4
261 /* move flash to 0x50000000 */
262 ldr r2, =IXP425_EXP_CFG0
264 bic r1, r1, #0x80000000
274 /* invalidate I & Data TLB */
275 mcr p15, 0, r0, c8, c7, 0
279 mrc p15, 0, r0, c1, c0, 0
280 orr r0, r0, #MMU_Control_I
281 mcr p15, 0, r0, c1, c0, 0
284 mrs r0,cpsr /* set the cpu to SVC32 mode */
285 bic r0,r0,#0x1f /* (superviser mode, M=10011) */
289 /* Set stackpointer in internal RAM to call board_init_f */
291 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
295 /*------------------------------------------------------------------------------*/
298 * void relocate_code (addr_sp, gd, addr_moni)
300 * This "function" does not return, instead it continues in RAM
301 * after relocating the monitor code.
306 mov r4, r0 /* save addr_sp */
307 mov r5, r1 /* save addr of gd */
308 mov r6, r2 /* save addr of destination */
309 mov r7, r2 /* save addr of destination */
311 /* Set up the stack */
318 sub r2, r3, r2 /* r2 <- size of armboot */
319 add r2, r0, r2 /* r2 <- source end address */
323 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
325 ldmia r0!, {r9-r10} /* copy from source address [r0] */
326 stmia r6!, {r9-r10} /* copy to target address [r1] */
327 cmp r0, r2 /* until source end address [r2] */
330 #ifndef CONFIG_PRELOADER
331 /* fix got entries */
332 ldr r1, _TEXT_BASE /* Text base */
333 mov r0, r7 /* reloc addr */
334 ldr r2, _got_start /* addr in Flash */
335 ldr r3, _got_end /* addr in Flash */
350 #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
353 #ifndef CONFIG_PRELOADER
356 ldr r3, _TEXT_BASE /* Text base */
357 mov r4, r7 /* reloc addr */
362 mov r2, #0x00000000 /* clear */
364 clbss_l:str r2, [r0] /* clear loop... */
374 * We are done. Do not return, instead branch to second part of board
375 * initialization, now running from RAM.
378 ldr r2, _board_init_r
380 add r2, r2, r7 /* position from board_init_r in RAM */
381 /* setup parameters for board_init_r */
382 mov r0, r5 /* gd_t */
383 mov r1, r7 /* dest_addr */
388 _board_init_r: .word board_init_r
391 /****************************************************************************/
393 /* Interrupt handling */
395 /****************************************************************************/
397 /* IRQ stack frame */
399 #define S_FRAME_SIZE 72
421 #define MODE_SVC 0x13
423 /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
425 .macro bad_save_user_regs
426 sub sp, sp, #S_FRAME_SIZE
427 stmia sp, {r0 - r12} /* Calling r0-r12 */
430 ldr r2, IRQ_STACK_START_IN
431 ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
432 add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
436 stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
441 /* use irq_save_user_regs / irq_restore_user_regs for */
442 /* IRQ/FIQ handling */
444 .macro irq_save_user_regs
445 sub sp, sp, #S_FRAME_SIZE
446 stmia sp, {r0 - r12} /* Calling r0-r12 */
448 stmdb r8, {sp, lr}^ /* Calling SP, LR */
449 str lr, [r8, #0] /* Save calling PC */
451 str r6, [r8, #4] /* Save CPSR */
452 str r0, [r8, #8] /* Save OLD_R0 */
456 .macro irq_restore_user_regs
457 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
459 ldr lr, [sp, #S_PC] @ Get PC
460 add sp, sp, #S_FRAME_SIZE
461 subs pc, lr, #4 @ return & move spsr_svc into cpsr
465 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
467 str lr, [r13] @ save caller lr / spsr
471 mov r13, #MODE_SVC @ prepare SVC-Mode
477 .macro get_irq_stack @ setup IRQ stack
478 ldr sp, IRQ_STACK_START
481 .macro get_fiq_stack @ setup FIQ stack
482 ldr sp, FIQ_STACK_START
486 /****************************************************************************/
488 /* exception handlers */
490 /****************************************************************************/
493 undefined_instruction:
496 bl do_undefined_instruction
502 bl do_software_interrupt
522 #ifdef CONFIG_USE_IRQ
529 irq_restore_user_regs
534 irq_save_user_regs /* someone ought to write a more */
535 bl do_fiq /* effiction fiq_save_user_regs */
536 irq_restore_user_regs
554 /****************************************************************************/
556 /* Reset function: Use Watchdog to reset */
558 /****************************************************************************/
580 #ifdef CONFIG_USE_IRQ
582 .LC0: .word loops_per_jiffy
593 ldr r2, [r2] @ max = 0x0fffffff
594 mov r0, r0, lsr #11 @ max = 0x00003fff
595 mov r2, r2, lsr #11 @ max = 0x0003ffff
596 mul r0, r2, r0 @ max = 2^32-1
604 #endif /* CONFIG_USE_IRQ */