2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm-offsets.h>
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
50 _undefined_instruction: .word undefined_instruction
51 _software_interrupt: .word software_interrupt
52 _prefetch_abort: .word prefetch_abort
53 _data_abort: .word data_abort
54 _not_used: .word not_used
58 .balignl 16,0xdeadbeef
62 *************************************************************************
64 * Startup Code (reset vector)
66 * do important init only if we don't start from memory!
67 * relocate armboot to ram
69 * jump to second stage
71 *************************************************************************
76 .word CONFIG_SYS_TEXT_BASE
78 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
85 * These are defined in the board-specific linker script.
96 /* IRQ stack memory (calculated at run-time) */
97 .globl IRQ_STACK_START
101 /* IRQ stack memory (calculated at run-time) */
102 .globl FIQ_STACK_START
107 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
108 /* IRQ stack memory (calculated at run-time) + 8 bytes */
109 .globl IRQ_STACK_START_IN
113 .globl _datarel_start
115 .word __datarel_start
117 .globl _datarelrolocal_start
118 _datarelrolocal_start:
119 .word __datarelrolocal_start
121 .globl _datarellocal_start
123 .word __datarellocal_start
125 .globl _datarelro_start
127 .word __datarelro_start
138 * the actual reset code
143 * set the cpu to SVC32 mode
150 #define pWDTCTL 0x80001400 /* Watchdog Timer control register */
151 #define pINTENC 0x8000050C /* Interupt-Controller enable clear register */
152 #define pCLKSET 0x80000420 /* clock divisor register */
154 /* disable watchdog, set watchdog control register to
155 * all zeros (default reset)
162 * mask all IRQs by setting all bits in the INTENC register (default)
168 /* FCLK:HCLK:PCLK = 1:2:2 */
169 /* default FCLK is 200 MHz, using 14.7456 MHz fin */
172 @ ldr r1, =0x0005ee39 @ 1: 2: 4
176 * we do sys-critical inits only at reboot,
177 * not when booting from ram!
179 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
183 /* Set stackpointer in internal RAM to call board_init_f */
185 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
189 /*------------------------------------------------------------------------------*/
192 * void relocate_code (addr_sp, gd, addr_moni)
194 * This "function" does not return, instead it continues in RAM
195 * after relocating the monitor code.
200 mov r4, r0 /* save addr_sp */
201 mov r5, r1 /* save addr of gd */
202 mov r6, r2 /* save addr of destination */
203 mov r7, r2 /* save addr of destination */
205 /* Set up the stack */
212 sub r2, r3, r2 /* r2 <- size of armboot */
213 add r2, r0, r2 /* r2 <- source end address */
217 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
219 ldmia r0!, {r9-r10} /* copy from source address [r0] */
220 stmia r6!, {r9-r10} /* copy to target address [r1] */
221 cmp r0, r2 /* until source end address [r2] */
224 #ifndef CONFIG_PRELOADER
225 /* fix got entries */
226 ldr r1, _TEXT_BASE /* Text base */
227 mov r0, r7 /* reloc addr */
228 ldr r2, _got_start /* addr in Flash */
229 ldr r3, _got_end /* addr in Flash */
244 #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
247 #ifndef CONFIG_PRELOADER
250 ldr r3, _TEXT_BASE /* Text base */
251 mov r4, r7 /* reloc addr */
256 mov r2, #0x00000000 /* clear */
258 clbss_l:str r2, [r0] /* clear loop... */
265 * We are done. Do not return, instead branch to second part of board
266 * initialization, now running from RAM.
269 ldr r2, _board_init_r
271 add r2, r2, r7 /* position from board_init_r in RAM */
272 /* setup parameters for board_init_r */
273 mov r0, r5 /* gd_t */
274 mov r1, r7 /* dest_addr */
279 _board_init_r: .word board_init_r
281 #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
283 * the actual reset code
288 * set the cpu to SVC32 mode
295 #define pWDTCTL 0x80001400 /* Watchdog Timer control register */
296 #define pINTENC 0x8000050C /* Interupt-Controller enable clear register */
297 #define pCLKSET 0x80000420 /* clock divisor register */
299 /* disable watchdog, set watchdog control register to
300 * all zeros (default reset)
307 * mask all IRQs by setting all bits in the INTENC register (default)
313 /* FCLK:HCLK:PCLK = 1:2:2 */
314 /* default FCLK is 200 MHz, using 14.7456 MHz fin */
317 @ ldr r1, =0x0005ee39 @ 1: 2: 4
321 * we do sys-critical inits only at reboot,
322 * not when booting from ram!
324 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
328 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
329 relocate: /* relocate U-Boot to RAM */
330 adr r0, _start /* r0 <- current position of code */
331 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
332 cmp r0, r1 /* don't reloc during debug */
335 ldr r2, _armboot_start
337 sub r2, r3, r2 /* r2 <- size of armboot */
338 add r2, r0, r2 /* r2 <- source end address */
341 ldmia r0!, {r3-r10} /* copy from source address [r0] */
342 stmia r1!, {r3-r10} /* copy to target address [r1] */
343 cmp r0, r2 /* until source end address [r2] */
345 #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
347 /* Set up the stack */
349 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
350 sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
351 sub r0, r0, #GENERATED_GBL_DATA_SIZE /* bdinfo */
352 #ifdef CONFIG_USE_IRQ
353 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
355 sub sp, r0, #12 /* leave 3 words for abort-stack */
356 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
359 ldr r0, _bss_start /* find start of bss segment */
360 @add r0, r0, #4 /* start at first byte of bss */
361 /* why inc. 4 bytes past then? */
362 ldr r1, _bss_end /* stop here */
363 mov r2, #0x00000000 /* clear */
365 clbss_l:str r2, [r0] /* clear loop... */
370 ldr pc, _start_armboot
372 _start_armboot: .word start_armboot
373 #endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
376 *************************************************************************
378 * CPU_init_critical registers
380 * setup important registers
381 * setup memory timing
383 *************************************************************************
389 * flush v4 I/D caches
392 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
393 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
396 * disable MMU stuff and caches
398 mrc p15, 0, r0, c1, c0, 0
399 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
400 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
401 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
402 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
403 orr r0, r0, #0x40000000 @ set bit 30 (nF) notFastBus
404 mcr p15, 0, r0, c1, c0, 0
408 * before relocating, we have to setup RAM timing
409 * because memory timing is board-dependend, you will
410 * find a lowlevel_init.S in your board directory.
420 *************************************************************************
424 *************************************************************************
430 #define S_FRAME_SIZE 72
452 #define MODE_SVC 0x13
456 * use bad_save_user_regs for abort/prefetch/undef/swi ...
457 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
460 .macro bad_save_user_regs
461 sub sp, sp, #S_FRAME_SIZE
462 stmia sp, {r0 - r12} @ Calling r0-r12
463 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
464 ldr r2, _armboot_start
465 sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
466 sub r2, r2, #(GENERATED_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
468 ldr r2, IRQ_STACK_START_IN
470 ldmia r2, {r2 - r3} @ get pc, cpsr
471 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
475 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
479 .macro irq_save_user_regs
480 sub sp, sp, #S_FRAME_SIZE
481 stmia sp, {r0 - r12} @ Calling r0-r12
483 stmdb r8, {sp, lr}^ @ Calling SP, LR
484 str lr, [r8, #0] @ Save calling PC
486 str r6, [r8, #4] @ Save CPSR
487 str r0, [r8, #8] @ Save OLD_R0
491 .macro irq_restore_user_regs
492 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
494 ldr lr, [sp, #S_PC] @ Get PC
495 add sp, sp, #S_FRAME_SIZE
496 subs pc, lr, #4 @ return & move spsr_svc into cpsr
500 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
501 ldr r13, _armboot_start @ setup our mode stack
502 sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
503 sub r13, r13, #(GENERATED_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
505 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
508 str lr, [r13] @ save caller lr / spsr
512 mov r13, #MODE_SVC @ prepare SVC-Mode
519 .macro get_irq_stack @ setup IRQ stack
520 ldr sp, IRQ_STACK_START
523 .macro get_fiq_stack @ setup FIQ stack
524 ldr sp, FIQ_STACK_START
531 undefined_instruction:
534 bl do_undefined_instruction
540 bl do_software_interrupt
560 #ifdef CONFIG_USE_IRQ
567 irq_restore_user_regs
572 /* someone ought to write a more effiction fiq_save_user_regs */
575 irq_restore_user_regs
596 bl disable_interrupts
598 /* Disable watchdog */
607 /* Enable the watchdog */