2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 *************************************************************************
35 * Jump vector table as in table 3.1 in [1]
37 *************************************************************************
43 ldr pc, _undefined_instruction
44 ldr pc, _software_interrupt
45 ldr pc, _prefetch_abort
51 _undefined_instruction: .word undefined_instruction
52 _software_interrupt: .word software_interrupt
53 _prefetch_abort: .word prefetch_abort
54 _data_abort: .word data_abort
55 _not_used: .word not_used
59 .balignl 16,0xdeadbeef
63 *************************************************************************
65 * Startup Code (reset vector)
67 * do important init only if we don't start from memory!
68 * relocate armboot to ram
70 * jump to second stage
72 *************************************************************************
79 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
86 * These are defined in the board-specific linker script.
97 /* IRQ stack memory (calculated at run-time) */
98 .globl IRQ_STACK_START
102 /* IRQ stack memory (calculated at run-time) */
103 .globl FIQ_STACK_START
108 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
109 /* IRQ stack memory (calculated at run-time) + 8 bytes */
110 .globl IRQ_STACK_START_IN
114 .globl _datarel_start
116 .word __datarel_start
118 .globl _datarelrolocal_start
119 _datarelrolocal_start:
120 .word __datarelrolocal_start
122 .globl _datarellocal_start
124 .word __datarellocal_start
126 .globl _datarelro_start
128 .word __datarelro_start
139 * the actual reset code
144 * set the cpu to SVC32 mode
151 #define pWDTCTL 0x80001400 /* Watchdog Timer control register */
152 #define pINTENC 0x8000050C /* Interupt-Controller enable clear register */
153 #define pCLKSET 0x80000420 /* clock divisor register */
155 /* disable watchdog, set watchdog control register to
156 * all zeros (default reset)
163 * mask all IRQs by setting all bits in the INTENC register (default)
169 /* FCLK:HCLK:PCLK = 1:2:2 */
170 /* default FCLK is 200 MHz, using 14.7456 MHz fin */
173 @ ldr r1, =0x0005ee39 @ 1: 2: 4
177 * we do sys-critical inits only at reboot,
178 * not when booting from ram!
180 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
184 /* Set stackpointer in internal RAM to call board_init_f */
186 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
190 /*------------------------------------------------------------------------------*/
193 * void relocate_code (addr_sp, gd, addr_moni)
195 * This "function" does not return, instead it continues in RAM
196 * after relocating the monitor code.
201 mov r4, r0 /* save addr_sp */
202 mov r5, r1 /* save addr of gd */
203 mov r6, r2 /* save addr of destination */
204 mov r7, r2 /* save addr of destination */
206 /* Set up the stack */
213 sub r2, r3, r2 /* r2 <- size of armboot */
214 add r2, r0, r2 /* r2 <- source end address */
218 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
220 ldmia r0!, {r9-r10} /* copy from source address [r0] */
221 stmia r6!, {r9-r10} /* copy to target address [r1] */
222 cmp r0, r2 /* until source end address [r2] */
225 #ifndef CONFIG_PRELOADER
226 /* fix got entries */
227 ldr r1, _TEXT_BASE /* Text base */
228 mov r0, r7 /* reloc addr */
229 ldr r2, _got_start /* addr in Flash */
230 ldr r3, _got_end /* addr in Flash */
245 #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
248 #ifndef CONFIG_PRELOADER
251 ldr r3, _TEXT_BASE /* Text base */
252 mov r4, r7 /* reloc addr */
257 mov r2, #0x00000000 /* clear */
259 clbss_l:str r2, [r0] /* clear loop... */
266 * We are done. Do not return, instead branch to second part of board
267 * initialization, now running from RAM.
270 ldr r2, _board_init_r
272 add r2, r2, r7 /* position from board_init_r in RAM */
273 /* setup parameters for board_init_r */
274 mov r0, r5 /* gd_t */
275 mov r1, r7 /* dest_addr */
280 _board_init_r: .word board_init_r
282 #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
284 * the actual reset code
289 * set the cpu to SVC32 mode
296 #define pWDTCTL 0x80001400 /* Watchdog Timer control register */
297 #define pINTENC 0x8000050C /* Interupt-Controller enable clear register */
298 #define pCLKSET 0x80000420 /* clock divisor register */
300 /* disable watchdog, set watchdog control register to
301 * all zeros (default reset)
308 * mask all IRQs by setting all bits in the INTENC register (default)
314 /* FCLK:HCLK:PCLK = 1:2:2 */
315 /* default FCLK is 200 MHz, using 14.7456 MHz fin */
318 @ ldr r1, =0x0005ee39 @ 1: 2: 4
322 * we do sys-critical inits only at reboot,
323 * not when booting from ram!
325 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
329 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
330 relocate: /* relocate U-Boot to RAM */
331 adr r0, _start /* r0 <- current position of code */
332 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
333 cmp r0, r1 /* don't reloc during debug */
336 ldr r2, _armboot_start
338 sub r2, r3, r2 /* r2 <- size of armboot */
339 add r2, r0, r2 /* r2 <- source end address */
342 ldmia r0!, {r3-r10} /* copy from source address [r0] */
343 stmia r1!, {r3-r10} /* copy to target address [r1] */
344 cmp r0, r2 /* until source end address [r2] */
346 #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
348 /* Set up the stack */
350 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
351 sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
352 sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
353 #ifdef CONFIG_USE_IRQ
354 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
356 sub sp, r0, #12 /* leave 3 words for abort-stack */
357 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
360 ldr r0, _bss_start /* find start of bss segment */
361 @add r0, r0, #4 /* start at first byte of bss */
362 /* why inc. 4 bytes past then? */
363 ldr r1, _bss_end /* stop here */
364 mov r2, #0x00000000 /* clear */
366 clbss_l:str r2, [r0] /* clear loop... */
371 ldr pc, _start_armboot
373 _start_armboot: .word start_armboot
374 #endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
377 *************************************************************************
379 * CPU_init_critical registers
381 * setup important registers
382 * setup memory timing
384 *************************************************************************
390 * flush v4 I/D caches
393 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
394 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
397 * disable MMU stuff and caches
399 mrc p15, 0, r0, c1, c0, 0
400 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
401 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
402 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
403 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
404 orr r0, r0, #0x40000000 @ set bit 30 (nF) notFastBus
405 mcr p15, 0, r0, c1, c0, 0
409 * before relocating, we have to setup RAM timing
410 * because memory timing is board-dependend, you will
411 * find a lowlevel_init.S in your board directory.
421 *************************************************************************
425 *************************************************************************
431 #define S_FRAME_SIZE 72
453 #define MODE_SVC 0x13
457 * use bad_save_user_regs for abort/prefetch/undef/swi ...
458 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
461 .macro bad_save_user_regs
462 sub sp, sp, #S_FRAME_SIZE
463 stmia sp, {r0 - r12} @ Calling r0-r12
464 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
465 ldr r2, _armboot_start
466 sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
467 sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
469 ldr r2, IRQ_STACK_START_IN
471 ldmia r2, {r2 - r3} @ get pc, cpsr
472 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
476 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
480 .macro irq_save_user_regs
481 sub sp, sp, #S_FRAME_SIZE
482 stmia sp, {r0 - r12} @ Calling r0-r12
484 stmdb r8, {sp, lr}^ @ Calling SP, LR
485 str lr, [r8, #0] @ Save calling PC
487 str r6, [r8, #4] @ Save CPSR
488 str r0, [r8, #8] @ Save OLD_R0
492 .macro irq_restore_user_regs
493 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
495 ldr lr, [sp, #S_PC] @ Get PC
496 add sp, sp, #S_FRAME_SIZE
497 subs pc, lr, #4 @ return & move spsr_svc into cpsr
501 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
502 ldr r13, _armboot_start @ setup our mode stack
503 sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
504 sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
506 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
509 str lr, [r13] @ save caller lr / spsr
513 mov r13, #MODE_SVC @ prepare SVC-Mode
520 .macro get_irq_stack @ setup IRQ stack
521 ldr sp, IRQ_STACK_START
524 .macro get_fiq_stack @ setup FIQ stack
525 ldr sp, FIQ_STACK_START
532 undefined_instruction:
535 bl do_undefined_instruction
541 bl do_software_interrupt
561 #ifdef CONFIG_USE_IRQ
568 irq_restore_user_regs
573 /* someone ought to write a more effiction fiq_save_user_regs */
576 irq_restore_user_regs
597 bl disable_interrupts
599 /* Disable watchdog */
608 /* Enable the watchdog */