2 * armboot - Startup Code for SA1100 CPU
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm-offsets.h>
33 *************************************************************************
35 * Jump vector table as in table 3.1 in [1]
37 *************************************************************************
43 ldr pc, _undefined_instruction
44 ldr pc, _software_interrupt
45 ldr pc, _prefetch_abort
51 _undefined_instruction: .word undefined_instruction
52 _software_interrupt: .word software_interrupt
53 _prefetch_abort: .word prefetch_abort
54 _data_abort: .word data_abort
55 _not_used: .word not_used
59 .balignl 16,0xdeadbeef
63 *************************************************************************
65 * Startup Code (reset vector)
67 * do important init only if we don't start from memory!
68 * relocate armboot to ram
70 * jump to second stage
72 *************************************************************************
77 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
78 .word CONFIG_SPL_TEXT_BASE
80 .word CONFIG_SYS_TEXT_BASE
84 * These are defined in the board-specific linker script.
85 * Subtracting _start from them lets the linker put their
86 * relative position in the executable instead of leaving
91 .word __bss_start - _start
95 .word __bss_end - _start
101 #ifdef CONFIG_USE_IRQ
102 /* IRQ stack memory (calculated at run-time) */
103 .globl IRQ_STACK_START
107 /* IRQ stack memory (calculated at run-time) */
108 .globl FIQ_STACK_START
113 /* IRQ stack memory (calculated at run-time) + 8 bytes */
114 .globl IRQ_STACK_START_IN
119 * the actual reset code
124 * set the cpu to SVC32 mode
132 * we do sys-critical inits only at reboot,
133 * not when booting from ram!
135 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
141 /*------------------------------------------------------------------------------*/
144 * void relocate_code (addr_sp, gd, addr_moni)
146 * This function relocates the monitor code.
150 mov r4, r0 /* save addr_sp */
151 mov r5, r1 /* save addr of gd */
152 mov r6, r2 /* save addr of destination */
156 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
157 beq relocate_done /* skip relocation */
158 mov r1, r6 /* r1 <- scratch for copy_loop */
159 ldr r3, _bss_start_ofs
160 add r2, r0, r3 /* r2 <- source end address */
163 ldmia r0!, {r9-r10} /* copy from source address [r0] */
164 stmia r1!, {r9-r10} /* copy to target address [r1] */
165 cmp r0, r2 /* until source end address [r2] */
168 #ifndef CONFIG_SPL_BUILD
170 * fix .rel.dyn relocations
172 ldr r0, _TEXT_BASE /* r0 <- Text base */
173 sub r9, r6, r0 /* r9 <- relocation offset */
174 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
175 add r10, r10, r0 /* r10 <- sym table in FLASH */
176 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
177 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
178 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
179 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
181 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
182 add r0, r0, r9 /* r0 <- location to fix up in RAM */
185 cmp r7, #23 /* relative fixup? */
187 cmp r7, #2 /* absolute fixup? */
189 /* ignore unknown type of fixup */
192 /* absolute fix: set location to (offset) symbol value */
193 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
194 add r1, r10, r1 /* r1 <- address of symbol in table */
195 ldr r1, [r1, #4] /* r1 <- symbol value */
196 add r1, r1, r9 /* r1 <- relocated sym addr */
199 /* relative fix: increase location by offset */
204 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
214 .word __rel_dyn_start - _start
216 .word __rel_dyn_end - _start
218 .word __dynsym_start - _start
220 .globl c_runtime_cpu_setup
226 *************************************************************************
228 * CPU_init_critical registers
230 * setup important registers
231 * setup memory timing
233 *************************************************************************
237 /* Interrupt-Controller base address */
238 IC_BASE: .word 0x90050000
242 /* Reset-Controller */
243 RST_BASE: .word 0x90030000
249 PWR_BASE: .word 0x90020000
252 cpuspeed: .word CONFIG_SYS_CPUSPEED
263 /* set clock speed */
269 * before relocating, we have to setup RAM timing
270 * because memory timing is board-dependend, you will
271 * find a lowlevel_init.S in your board directory.
278 * disable MMU stuff and enable I-cache
281 bic r0, r0, #0x00002000 @ clear bit 13 (X)
282 bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM)
283 orr r0, r0, #0x00001000 @ set bit 12 (I) Icache
284 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
288 * flush v4 I/D caches
291 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
292 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
298 *************************************************************************
302 *************************************************************************
308 #define S_FRAME_SIZE 72
330 #define MODE_SVC 0x13
334 * use bad_save_user_regs for abort/prefetch/undef/swi ...
335 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
338 .macro bad_save_user_regs
339 sub sp, sp, #S_FRAME_SIZE
340 stmia sp, {r0 - r12} @ Calling r0-r12
343 ldr r2, IRQ_STACK_START_IN
344 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
345 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
349 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
353 .macro irq_save_user_regs
354 sub sp, sp, #S_FRAME_SIZE
355 stmia sp, {r0 - r12} @ Calling r0-r12
357 stmdb r8, {sp, lr}^ @ Calling SP, LR
358 str lr, [r8, #0] @ Save calling PC
360 str r6, [r8, #4] @ Save CPSR
361 str r0, [r8, #8] @ Save OLD_R0
365 .macro irq_restore_user_regs
366 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
368 ldr lr, [sp, #S_PC] @ Get PC
369 add sp, sp, #S_FRAME_SIZE
370 subs pc, lr, #4 @ return & move spsr_svc into cpsr
374 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
376 str lr, [r13] @ save caller lr / spsr
380 mov r13, #MODE_SVC @ prepare SVC-Mode
386 .macro get_irq_stack @ setup IRQ stack
387 ldr sp, IRQ_STACK_START
390 .macro get_fiq_stack @ setup FIQ stack
391 ldr sp, FIQ_STACK_START
398 undefined_instruction:
401 bl do_undefined_instruction
407 bl do_software_interrupt
427 #ifdef CONFIG_USE_IRQ
434 irq_restore_user_regs
439 /* someone ought to write a more effiction fiq_save_user_regs */
442 irq_restore_user_regs
464 mov r1, #0x0 @ set bit 3-0 ...
465 str r1, [r0, #RCSR] @ ... to clear in RCSR
467 str r1, [r0, #RSRR] @ and perform reset
468 b reset_cpu @ silly, but repeat endlessly