2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * SPDX-License-Identifier: GPL-2.0+ or X11
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3188-cru.h>
11 #include "rk3xxx.dtsi"
14 compatible = "rockchip,rk3188";
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
37 clock-latency = <40000>;
38 clocks = <&cru ARMCLK>;
42 compatible = "arm,cortex-a9";
43 next-level-cache = <&L2>;
48 compatible = "arm,cortex-a9";
49 next-level-cache = <&L2>;
54 compatible = "arm,cortex-a9";
55 next-level-cache = <&L2>;
61 compatible = "mmio-sram";
62 reg = <0x10080000 0x8000>;
65 ranges = <0 0x10080000 0x8000>;
68 compatible = "rockchip,rk3066-smp-sram";
74 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
75 reg = <0x1011a000 0x2000>;
76 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&i2s0_bus>;
81 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
82 dma-names = "tx", "rx";
83 clock-names = "i2s_hclk", "i2s_clk";
84 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
85 rockchip,playback-channels = <2>;
86 rockchip,capture-channels = <2>;
90 spdif: sound@1011e000 {
91 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
92 reg = <0x1011e000 0x2000>;
93 #sound-dai-cells = <0>;
94 clock-names = "hclk", "mclk";
95 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
98 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&spdif_tx>;
104 cru: clock-controller@20000000 {
105 compatible = "rockchip,rk3188-cru";
106 reg = <0x20000000 0x1000>;
107 rockchip,grf = <&grf>;
113 efuse: efuse@20010000 {
114 compatible = "rockchip,rockchip-efuse";
115 reg = <0x20010000 0x4000>;
116 #address-cells = <1>;
118 clocks = <&cru PCLK_EFUSE>;
119 clock-names = "pclk_efuse";
121 cpu_leakage: cpu_leakage@17 {
126 timer3: timer@2000e000 {
127 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
128 reg = <0x2000e000 0x20>;
129 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
133 compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
134 rockchip,grf = <&grf>;
135 #address-cells = <1>;
139 usbphy0: usb-phy@10c {
142 clocks = <&cru SCLK_OTGPHY0>;
143 clock-names = "phyclk";
147 usbphy1: usb-phy@11c {
150 clocks = <&cru SCLK_OTGPHY1>;
151 clock-names = "phyclk";
157 compatible = "rockchip,rk3188-pinctrl";
158 rockchip,grf = <&grf>;
159 rockchip,pmu = <&pmu>;
161 #address-cells = <1>;
165 gpio0: gpio0@2000a000 {
166 compatible = "rockchip,gpio-bank";
167 reg = <0x2000a000 0x100>;
168 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
169 clocks = <&cru PCLK_GPIO0>;
174 interrupt-controller;
175 #interrupt-cells = <2>;
178 gpio1: gpio1@2003c000 {
179 compatible = "rockchip,gpio-bank";
180 reg = <0x2003c000 0x100>;
181 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&cru PCLK_GPIO1>;
187 interrupt-controller;
188 #interrupt-cells = <2>;
191 gpio2: gpio2@2003e000 {
192 compatible = "rockchip,gpio-bank";
193 reg = <0x2003e000 0x100>;
194 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&cru PCLK_GPIO2>;
200 interrupt-controller;
201 #interrupt-cells = <2>;
204 gpio3: gpio3@20080000 {
205 compatible = "rockchip,gpio-bank";
206 reg = <0x20080000 0x100>;
207 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&cru PCLK_GPIO3>;
213 interrupt-controller;
214 #interrupt-cells = <2>;
217 pcfg_pull_up: pcfg_pull_up {
221 pcfg_pull_down: pcfg_pull_down {
225 pcfg_pull_none: pcfg_pull_none {
231 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
235 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
239 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
243 * The data pins are shared between nandc and emmc and
244 * not accessible through pinctrl. Also they should've
245 * been already set correctly by firmware, as
246 * flash/emmc is the boot-device.
251 emac_xfer: emac-xfer {
252 rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
253 <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
254 <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
255 <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
256 <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
257 <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
258 <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
259 <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
262 emac_mdio: emac-mdio {
263 rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
264 <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
269 i2c0_xfer: i2c0-xfer {
270 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
271 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
276 i2c1_xfer: i2c1-xfer {
277 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
278 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
283 i2c2_xfer: i2c2-xfer {
284 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
285 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
290 i2c3_xfer: i2c3-xfer {
291 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
292 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
297 i2c4_xfer: i2c4-xfer {
298 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
299 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
305 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
311 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
317 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
323 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
329 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
332 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
335 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
338 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
341 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
347 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
350 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
353 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
356 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
359 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
364 uart0_xfer: uart0-xfer {
365 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
366 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
369 uart0_cts: uart0-cts {
370 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
373 uart0_rts: uart0-rts {
374 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
379 uart1_xfer: uart1-xfer {
380 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
381 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
384 uart1_cts: uart1-cts {
385 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
388 uart1_rts: uart1-rts {
389 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
394 uart2_xfer: uart2-xfer {
395 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
396 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
398 /* no rts / cts for uart2 */
402 uart3_xfer: uart3-xfer {
403 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
404 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
407 uart3_cts: uart3-cts {
408 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
411 uart3_rts: uart3-rts {
412 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
418 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
422 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
426 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
430 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
434 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
437 sd0_bus1: sd0-bus-width1 {
438 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
441 sd0_bus4: sd0-bus-width4 {
442 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
443 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
444 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
445 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
451 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
455 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
459 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
463 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
466 sd1_bus1: sd1-bus-width1 {
467 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
470 sd1_bus4: sd1-bus-width4 {
471 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
472 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
473 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
474 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
480 rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
481 <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
482 <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
483 <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
484 <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
485 <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
491 rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
498 compatible = "rockchip,rk3188-emac";
502 interrupts = <GIC_PPI 11 0xf04>;
506 compatible = "rockchip,rk3188-grf", "syscon";
510 interrupts = <GIC_PPI 13 0xf04>;
514 compatible = "rockchip,rk3188-i2c";
515 pinctrl-names = "default";
516 pinctrl-0 = <&i2c0_xfer>;
520 compatible = "rockchip,rk3188-i2c";
521 pinctrl-names = "default";
522 pinctrl-0 = <&i2c1_xfer>;
526 compatible = "rockchip,rk3188-i2c";
527 pinctrl-names = "default";
528 pinctrl-0 = <&i2c2_xfer>;
532 compatible = "rockchip,rk3188-i2c";
533 pinctrl-names = "default";
534 pinctrl-0 = <&i2c3_xfer>;
538 compatible = "rockchip,rk3188-i2c";
539 pinctrl-names = "default";
540 pinctrl-0 = <&i2c4_xfer>;
544 compatible = "rockchip,rk3188-pmu", "syscon";
548 pinctrl-names = "default";
549 pinctrl-0 = <&pwm0_out>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&pwm1_out>;
558 pinctrl-names = "default";
559 pinctrl-0 = <&pwm2_out>;
563 pinctrl-names = "default";
564 pinctrl-0 = <&pwm3_out>;
568 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
569 pinctrl-names = "default";
570 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
574 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
575 pinctrl-names = "default";
576 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
580 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
581 pinctrl-names = "default";
582 pinctrl-0 = <&uart0_xfer>;
586 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
587 pinctrl-names = "default";
588 pinctrl-0 = <&uart1_xfer>;
592 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
593 pinctrl-names = "default";
594 pinctrl-0 = <&uart2_xfer>;
598 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
599 pinctrl-names = "default";
600 pinctrl-0 = <&uart3_xfer>;
604 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";