2 * SPDX-License-Identifier: GPL-2.0+
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3288-cru.h>
10 #include <dt-bindings/power-domain/rk3288.h>
11 #include <dt-bindings/thermal/thermal.h>
12 #include <dt-bindings/video/rk3288.h>
13 #include "skeleton.dtsi"
16 compatible = "rockchip,rk3288";
18 interrupt-parent = <&gic>;
56 enable-method = "rockchip,rk3066-smp";
57 rockchip,pmu = <&pmu>;
61 compatible = "arm,cortex-a12";
79 #cooling-cells = <2>; /* min followed by max */
80 clock-latency = <40000>;
81 clocks = <&cru ARMCLK>;
82 resets = <&cru SRST_CORE0>;
86 compatible = "arm,cortex-a12";
88 resets = <&cru SRST_CORE1>;
92 compatible = "arm,cortex-a12";
94 resets = <&cru SRST_CORE2>;
98 compatible = "arm,cortex-a12";
100 resets = <&cru SRST_CORE3>;
105 compatible = "arm,amba-bus";
106 #address-cells = <1>;
110 dmac_peri: dma-controller@ff250000 {
111 compatible = "arm,pl330", "arm,primecell";
113 reg = <0xff250000 0x4000>;
114 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
117 clocks = <&cru ACLK_DMAC2>;
118 clock-names = "apb_pclk";
121 dmac_bus_ns: dma-controller@ff600000 {
122 compatible = "arm,pl330", "arm,primecell";
124 reg = <0xff600000 0x4000>;
125 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
128 clocks = <&cru ACLK_DMAC1>;
129 clock-names = "apb_pclk";
133 dmac_bus_s: dma-controller@ffb20000 {
134 compatible = "arm,pl330", "arm,primecell";
136 reg = <0xffb20000 0x4000>;
137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
140 clocks = <&cru ACLK_DMAC1>;
141 clock-names = "apb_pclk";
146 compatible = "fixed-clock";
147 clock-frequency = <24000000>;
148 clock-output-names = "xin24m";
153 arm,use-physical-timer;
154 compatible = "arm,armv7-timer";
155 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
156 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
157 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
158 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
159 clock-frequency = <24000000>;
164 compatible = "rockchip,display-subsystem";
165 ports = <&vopl_out>, <&vopb_out>;
168 sdmmc: dwmmc@ff0c0000 {
169 compatible = "rockchip,rk3288-dw-mshc";
170 max-frequency = <150000000>;
171 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
172 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
173 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
174 fifo-depth = <0x100>;
175 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
176 reg = <0xff0c0000 0x4000>;
180 sdio0: dwmmc@ff0d0000 {
181 compatible = "rockchip,rk3288-dw-mshc";
182 max-frequency = <150000000>;
183 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
184 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
185 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
186 fifo-depth = <0x100>;
187 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
188 reg = <0xff0d0000 0x4000>;
192 sdio1: dwmmc@ff0e0000 {
193 compatible = "rockchip,rk3288-dw-mshc";
194 max-frequency = <150000000>;
195 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
196 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
197 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
198 fifo-depth = <0x100>;
199 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
200 reg = <0xff0e0000 0x4000>;
204 emmc: dwmmc@ff0f0000 {
205 compatible = "rockchip,rk3288-dw-mshc";
206 max-frequency = <150000000>;
207 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
208 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
209 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
210 fifo-depth = <0x100>;
211 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
212 reg = <0xff0f0000 0x4000>;
216 saradc: saradc@ff100000 {
217 compatible = "rockchip,saradc";
218 reg = <0xff100000 0x100>;
219 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
220 #io-channel-cells = <1>;
221 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
222 clock-names = "saradc", "apb_pclk";
227 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
228 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
229 clock-names = "spiclk", "apb_pclk";
230 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
231 dma-names = "tx", "rx";
232 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
233 pinctrl-names = "default";
234 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
235 reg = <0xff110000 0x1000>;
236 #address-cells = <1>;
242 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
243 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
244 clock-names = "spiclk", "apb_pclk";
245 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
246 dma-names = "tx", "rx";
247 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
248 pinctrl-names = "default";
249 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
250 reg = <0xff120000 0x1000>;
251 #address-cells = <1>;
257 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
258 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
259 clock-names = "spiclk", "apb_pclk";
260 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
261 dma-names = "tx", "rx";
262 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
265 reg = <0xff130000 0x1000>;
266 #address-cells = <1>;
272 compatible = "rockchip,rk3288-i2c";
273 reg = <0xff140000 0x1000>;
274 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
275 #address-cells = <1>;
278 clocks = <&cru PCLK_I2C1>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&i2c1_xfer>;
285 compatible = "rockchip,rk3288-i2c";
286 reg = <0xff150000 0x1000>;
287 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
288 #address-cells = <1>;
291 clocks = <&cru PCLK_I2C3>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&i2c3_xfer>;
298 compatible = "rockchip,rk3288-i2c";
299 reg = <0xff160000 0x1000>;
300 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
301 #address-cells = <1>;
304 clocks = <&cru PCLK_I2C4>;
305 pinctrl-names = "default";
306 pinctrl-0 = <&i2c4_xfer>;
311 compatible = "rockchip,rk3288-i2c";
312 reg = <0xff170000 0x1000>;
313 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
314 #address-cells = <1>;
317 clocks = <&cru PCLK_I2C5>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&i2c5_xfer>;
322 uart0: serial@ff180000 {
323 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
324 reg = <0xff180000 0x100>;
325 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
328 clock-frequency = <24000000>;
329 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
330 clock-names = "baudclk", "apb_pclk";
331 pinctrl-names = "default";
332 pinctrl-0 = <&uart0_xfer>;
336 uart1: serial@ff190000 {
337 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
338 reg = <0xff190000 0x100>;
339 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
342 clock-frequency = <24000000>;
343 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
344 clock-names = "baudclk", "apb_pclk";
345 pinctrl-names = "default";
346 pinctrl-0 = <&uart1_xfer>;
350 uart2: serial@ff690000 {
351 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
352 reg = <0xff690000 0x100>;
353 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
356 clock-frequency = <24000000>;
357 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
358 clock-names = "baudclk", "apb_pclk";
359 pinctrl-names = "default";
360 pinctrl-0 = <&uart2_xfer>;
363 uart3: serial@ff1b0000 {
364 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
365 reg = <0xff1b0000 0x100>;
366 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
369 clock-frequency = <24000000>;
370 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
371 clock-names = "baudclk", "apb_pclk";
372 pinctrl-names = "default";
373 pinctrl-0 = <&uart3_xfer>;
377 uart4: serial@ff1c0000 {
378 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
379 reg = <0xff1c0000 0x100>;
380 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
383 clock-frequency = <24000000>;
384 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
385 clock-names = "baudclk", "apb_pclk";
386 pinctrl-names = "default";
387 pinctrl-0 = <&uart4_xfer>;
390 thermal: thermal-zones {
391 #include "rk3288-thermal.dtsi"
394 tsadc: tsadc@ff280000 {
395 compatible = "rockchip,rk3288-tsadc";
396 reg = <0xff280000 0x100>;
397 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
399 clock-names = "tsadc", "apb_pclk";
400 resets = <&cru SRST_TSADC>;
401 reset-names = "tsadc-apb";
402 pinctrl-names = "otp_out";
403 pinctrl-0 = <&otp_out>;
404 #thermal-sensor-cells = <1>;
405 hw-shut-temp = <125000>;
409 gmac: ethernet@ff290000 {
410 compatible = "rockchip,rk3288-gmac";
411 reg = <0xff290000 0x10000>;
412 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
413 interrupt-names = "macirq";
414 rockchip,grf = <&grf>;
415 clocks = <&cru SCLK_MAC>,
416 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
417 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
418 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
419 clock-names = "stmmaceth",
420 "mac_clk_rx", "mac_clk_tx",
421 "clk_mac_ref", "clk_mac_refout",
422 "aclk_mac", "pclk_mac";
425 usb_host0_ehci: usb@ff500000 {
426 compatible = "generic-ehci";
427 reg = <0xff500000 0x100>;
428 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&cru HCLK_USBHOST0>;
430 clock-names = "usbhost";
436 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
438 usb_host1: usb@ff540000 {
439 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
441 reg = <0xff540000 0x40000>;
442 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&cru HCLK_USBHOST1>;
446 phy-names = "usb2-phy";
450 usb_otg: usb@ff580000 {
451 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
453 reg = <0xff580000 0x40000>;
454 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&cru HCLK_OTG0>;
459 phy-names = "usb2-phy";
463 usb_hsic: usb@ff5c0000 {
464 compatible = "generic-ehci";
465 reg = <0xff5c0000 0x100>;
466 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&cru HCLK_HSIC>;
468 clock-names = "usbhost";
474 compatible = "rockchip,rk3288-dmc", "syscon";
475 rockchip,cru = <&cru>;
476 rockchip,grf = <&grf>;
477 rockchip,pmu = <&pmu>;
478 rockchip,sgrf = <&sgrf>;
479 rockchip,noc = <&noc>;
480 reg = <0xff610000 0x3fc
484 rockchip,sram = <&ddr_sram>;
485 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
486 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
488 clock-names = "pclk_ddrupctl0", "pclk_publ0",
489 "pclk_ddrupctl1", "pclk_publ1",
494 compatible = "rockchip,rk3288-i2c";
495 reg = <0xff650000 0x1000>;
496 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
497 #address-cells = <1>;
500 clocks = <&cru PCLK_I2C0>;
501 pinctrl-names = "default";
502 pinctrl-0 = <&i2c0_xfer>;
507 compatible = "rockchip,rk3288-i2c";
508 reg = <0xff660000 0x1000>;
509 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
510 #address-cells = <1>;
513 clocks = <&cru PCLK_I2C2>;
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2c2_xfer>;
520 compatible = "rockchip,rk3288-pwm";
521 reg = <0xff680000 0x10>;
523 pinctrl-names = "default";
524 pinctrl-0 = <&pwm0_pin>;
525 clocks = <&cru PCLK_PWM>;
527 rockchip,grf = <&grf>;
532 compatible = "rockchip,rk3288-pwm";
533 reg = <0xff680010 0x10>;
535 pinctrl-names = "default";
536 pinctrl-0 = <&pwm1_pin>;
537 clocks = <&cru PCLK_PWM>;
539 rockchip,grf = <&grf>;
544 compatible = "rockchip,rk3288-pwm";
545 reg = <0xff680020 0x10>;
547 pinctrl-names = "default";
548 pinctrl-0 = <&pwm2_pin>;
549 clocks = <&cru PCLK_PWM>;
551 rockchip,grf = <&grf>;
556 compatible = "rockchip,rk3288-pwm";
557 reg = <0xff680030 0x10>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&pwm3_pin>;
561 clocks = <&cru PCLK_PWM>;
563 rockchip,grf = <&grf>;
567 bus_intmem@ff700000 {
568 compatible = "mmio-sram";
569 reg = <0xff700000 0x18000>;
570 #address-cells = <1>;
572 ranges = <0 0xff700000 0x18000>;
574 compatible = "rockchip,rk3066-smp-sram";
577 ddr_sram: ddr-sram@1000 {
578 compatible = "rockchip,rk3288-ddr-sram";
579 reg = <0x1000 0x4000>;
584 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
585 reg = <0xff720000 0x1000>;
588 pmu: power-management@ff730000 {
590 compatible = "rockchip,rk3288-pmu", "syscon";
591 reg = <0xff730000 0x100>;
594 sgrf: syscon@ff740000 {
596 compatible = "rockchip,rk3288-sgrf", "syscon";
597 reg = <0xff740000 0x1000>;
600 cru: clock-controller@ff760000 {
601 compatible = "rockchip,rk3288-cru";
602 reg = <0xff760000 0x1000>;
603 rockchip,grf = <&grf>;
607 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
608 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
609 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
610 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
612 assigned-clock-rates = <594000000>, <400000000>,
613 <500000000>, <300000000>,
614 <150000000>, <75000000>,
615 <300000000>, <150000000>,
619 grf: syscon@ff770000 {
621 compatible = "rockchip,rk3288-grf", "syscon";
622 reg = <0xff770000 0x1000>;
625 wdt: watchdog@ff800000 {
626 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
627 reg = <0xff800000 0x100>;
628 clocks = <&cru PCLK_WDT>;
629 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
633 spdif: sound@ff88b0000 {
634 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
635 reg = <0xff8b0000 0x10000>;
636 #sound-dai-cells = <0>;
637 clock-names = "hclk", "mclk";
638 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
639 dmas = <&dmac_bus_s 3>;
641 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
642 pinctrl-names = "default";
643 pinctrl-0 = <&spdif_tx>;
644 rockchip,grf = <&grf>;
649 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
650 reg = <0xff890000 0x10000>;
651 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
652 #address-cells = <1>;
654 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
655 dma-names = "tx", "rx";
656 clock-names = "i2s_hclk", "i2s_clk";
657 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
658 pinctrl-names = "default";
659 pinctrl-0 = <&i2s0_bus>;
665 compatible = "rockchip,rk3288-vop";
666 reg = <0xff930000 0x19c>;
667 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
669 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
670 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
671 reset-names = "axi", "ahb", "dclk";
672 iommus = <&vopb_mmu>;
673 power-domains = <&power RK3288_PD_VIO>;
676 #address-cells = <1>;
678 vopb_out_edp: endpoint@0 {
680 remote-endpoint = <&edp_in_vopb>;
682 vopb_out_hdmi: endpoint@1 {
684 remote-endpoint = <&hdmi_in_vopb>;
686 vopb_out_lvds: endpoint@2 {
688 remote-endpoint = <&lvds_in_vopb>;
690 vopb_out_mipi: endpoint@3 {
692 remote-endpoint = <&mipi_in_vopb>;
698 vopb_mmu: iommu@ff930300 {
699 compatible = "rockchip,iommu";
700 reg = <0xff930300 0x100>;
701 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
702 interrupt-names = "vopb_mmu";
703 power-domains = <&power RK3288_PD_VIO>;
709 compatible = "rockchip,rk3288-vop";
710 reg = <0xff940000 0x19c>;
711 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
713 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
714 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
715 reset-names = "axi", "ahb", "dclk";
716 iommus = <&vopl_mmu>;
717 power-domains = <&power RK3288_PD_VIO>;
721 #address-cells = <1>;
723 vopl_out_edp: endpoint@0 {
725 remote-endpoint = <&edp_in_vopl>;
727 vopl_out_hdmi: endpoint@1 {
729 remote-endpoint = <&hdmi_in_vopl>;
731 vopl_out_lvds: endpoint@2 {
733 remote-endpoint = <&lvds_in_vopl>;
735 vopl_out_mipi: endpoint@3 {
737 remote-endpoint = <&mipi_in_vopl>;
743 vopl_mmu: iommu@ff940300 {
744 compatible = "rockchip,iommu";
745 reg = <0xff940300 0x100>;
746 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
747 interrupt-names = "vopl_mmu";
748 power-domains = <&power RK3288_PD_VIO>;
754 compatible = "rockchip,rk3288-edp";
755 reg = <0xff970000 0x4000>;
756 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
758 rockchip,grf = <&grf>;
759 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
762 power-domains = <&power RK3288_PD_VIO>;
766 #address-cells = <1>;
768 edp_in_vopb: endpoint@0 {
770 remote-endpoint = <&vopb_out_edp>;
772 edp_in_vopl: endpoint@1 {
774 remote-endpoint = <&vopl_out_edp>;
780 hdmi: hdmi@ff980000 {
781 compatible = "rockchip,rk3288-dw-hdmi";
782 reg = <0xff980000 0x20000>;
784 ddc-i2c-bus = <&i2c5>;
785 rockchip,grf = <&grf>;
786 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
788 clock-names = "iahb", "isfr";
792 #address-cells = <1>;
794 hdmi_in_vopb: endpoint@0 {
796 remote-endpoint = <&vopb_out_hdmi>;
798 hdmi_in_vopl: endpoint@1 {
800 remote-endpoint = <&vopl_out_hdmi>;
806 lvds: lvds@ff96c000 {
807 compatible = "rockchip,rk3288-lvds";
808 reg = <0xff96c000 0x4000>;
809 clocks = <&cru PCLK_LVDS_PHY>;
810 clock-names = "pclk_lvds";
811 pinctrl-names = "default";
812 pinctrl-0 = <&lcdc0_ctl>;
813 rockchip,grf = <&grf>;
816 #address-cells = <1>;
820 #address-cells = <1>;
822 lvds_in_vopb: endpoint@0 {
824 remote-endpoint = <&vopb_out_lvds>;
826 lvds_in_vopl: endpoint@1 {
828 remote-endpoint = <&vopl_out_lvds>;
834 mipi_dsi0: mipi@ff960000 {
835 compatible = "rockchip,rk3288_mipi_dsi";
836 reg = <0xff960000 0x4000>;
837 clocks = <&cru PCLK_MIPI_DSI0>;
838 clock-names = "pclk_mipi";
839 /*pinctrl-names = "default";
840 pinctrl-0 = <&lcdc0_ctl>;*/
841 rockchip,grf = <&grf>;
842 #address-cells = <1>;
846 #address-cells = <1>;
850 #address-cells = <1>;
852 mipi_in_vopb: endpoint@0 {
854 remote-endpoint = <&vopb_out_mipi>;
856 mipi_in_vopl: endpoint@1 {
858 remote-endpoint = <&vopl_out_mipi>;
864 hdmi_audio: hdmi_audio {
865 compatible = "rockchip,rk3288-hdmi-audio";
866 i2s-controller = <&i2s>;
870 vpu: video-codec@ff9a0000 {
871 compatible = "rockchip,rk3288-vpu";
872 reg = <0xff9a0000 0x800>;
873 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
874 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
875 interrupt-names = "vepu", "vdpu";
876 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
877 clock-names = "aclk_vcodec", "hclk_vcodec";
878 power-domains = <&power RK3288_PD_VIDEO>;
882 vpu_mmu: iommu@ff9a0800 {
883 compatible = "rockchip,iommu";
884 reg = <0xff9a0800 0x100>;
885 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
886 interrupt-names = "vpu_mmu";
887 power-domains = <&power RK3288_PD_VIDEO>;
892 compatible = "arm,malit764",
896 reg = <0xffa30000 0x10000>;
897 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
898 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
899 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
900 interrupt-names = "JOB", "MMU", "GPU";
901 clocks = <&cru ACLK_GPU>;
902 clock-names = "aclk_gpu";
909 /* 500000 1200000 - See crosbug.com/p/33857 */
912 power-domains = <&power RK3288_PD_GPU>;
916 noc: syscon@ffac0000 {
918 compatible = "rockchip,rk3288-noc", "syscon";
919 reg = <0xffac0000 0x2000>;
922 efuse: efuse@ffb40000 {
923 compatible = "rockchip,rk3288-efuse";
924 reg = <0xffb40000 0x10000>;
928 gic: interrupt-controller@ffc01000 {
929 compatible = "arm,gic-400";
930 interrupt-controller;
931 #interrupt-cells = <3>;
932 #address-cells = <0>;
934 reg = <0xffc01000 0x1000>,
938 interrupts = <GIC_PPI 9 0xf04>;
942 compatible = "rockchip,rk3288-cpuidle";
946 compatible = "rockchip,rk3288-usb-phy";
947 rockchip,grf = <&grf>;
948 #address-cells = <1>;
955 clocks = <&cru SCLK_OTGPHY0>;
956 clock-names = "phyclk";
962 clocks = <&cru SCLK_OTGPHY1>;
963 clock-names = "phyclk";
969 clocks = <&cru SCLK_OTGPHY2>;
970 clock-names = "phyclk";
975 compatible = "rockchip,rk3288-pinctrl";
976 rockchip,grf = <&grf>;
977 rockchip,pmu = <&pmu>;
978 #address-cells = <1>;
982 gpio0: gpio0@ff750000 {
983 compatible = "rockchip,gpio-bank";
984 reg = <0xff750000 0x100>;
985 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
986 clocks = <&cru PCLK_GPIO0>;
991 interrupt-controller;
992 #interrupt-cells = <2>;
995 gpio1: gpio1@ff780000 {
996 compatible = "rockchip,gpio-bank";
997 reg = <0xff780000 0x100>;
998 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
999 clocks = <&cru PCLK_GPIO1>;
1004 interrupt-controller;
1005 #interrupt-cells = <2>;
1008 gpio2: gpio2@ff790000 {
1009 compatible = "rockchip,gpio-bank";
1010 reg = <0xff790000 0x100>;
1011 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1012 clocks = <&cru PCLK_GPIO2>;
1017 interrupt-controller;
1018 #interrupt-cells = <2>;
1021 gpio3: gpio3@ff7a0000 {
1022 compatible = "rockchip,gpio-bank";
1023 reg = <0xff7a0000 0x100>;
1024 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1025 clocks = <&cru PCLK_GPIO3>;
1030 interrupt-controller;
1031 #interrupt-cells = <2>;
1034 gpio4: gpio4@ff7b0000 {
1035 compatible = "rockchip,gpio-bank";
1036 reg = <0xff7b0000 0x100>;
1037 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1038 clocks = <&cru PCLK_GPIO4>;
1043 interrupt-controller;
1044 #interrupt-cells = <2>;
1047 gpio5: gpio5@ff7c0000 {
1048 compatible = "rockchip,gpio-bank";
1049 reg = <0xff7c0000 0x100>;
1050 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1051 clocks = <&cru PCLK_GPIO5>;
1056 interrupt-controller;
1057 #interrupt-cells = <2>;
1060 gpio6: gpio6@ff7d0000 {
1061 compatible = "rockchip,gpio-bank";
1062 reg = <0xff7d0000 0x100>;
1063 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1064 clocks = <&cru PCLK_GPIO6>;
1069 interrupt-controller;
1070 #interrupt-cells = <2>;
1073 gpio7: gpio7@ff7e0000 {
1074 compatible = "rockchip,gpio-bank";
1075 reg = <0xff7e0000 0x100>;
1076 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1077 clocks = <&cru PCLK_GPIO7>;
1082 interrupt-controller;
1083 #interrupt-cells = <2>;
1086 gpio8: gpio8@ff7f0000 {
1087 compatible = "rockchip,gpio-bank";
1088 reg = <0xff7f0000 0x100>;
1089 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1090 clocks = <&cru PCLK_GPIO8>;
1095 interrupt-controller;
1096 #interrupt-cells = <2>;
1099 pcfg_pull_up: pcfg-pull-up {
1103 pcfg_pull_down: pcfg-pull-down {
1107 pcfg_pull_none: pcfg-pull-none {
1111 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1113 drive-strength = <12>;
1117 global_pwroff: global-pwroff {
1118 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1121 ddrio_pwroff: ddrio-pwroff {
1122 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1125 ddr0_retention: ddr0-retention {
1126 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1129 ddr1_retention: ddr1-retention {
1130 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1135 i2c0_xfer: i2c0-xfer {
1136 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1137 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1142 i2c1_xfer: i2c1-xfer {
1143 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1144 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1149 i2c2_xfer: i2c2-xfer {
1150 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1151 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1156 i2c3_xfer: i2c3-xfer {
1157 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1158 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1163 i2c4_xfer: i2c4-xfer {
1164 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1165 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1170 i2c5_xfer: i2c5-xfer {
1171 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1172 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1177 i2s0_bus: i2s0-bus {
1178 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1179 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1180 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1181 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1182 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1183 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1188 lcdc0_ctl: lcdc0-ctl {
1189 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1190 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1191 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1192 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1197 sdmmc_clk: sdmmc-clk {
1198 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1201 sdmmc_cmd: sdmmc-cmd {
1202 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1205 sdmmc_cd: sdmcc-cd {
1206 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1209 sdmmc_bus1: sdmmc-bus1 {
1210 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1213 sdmmc_bus4: sdmmc-bus4 {
1214 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1215 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1216 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1217 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1222 sdio0_bus1: sdio0-bus1 {
1223 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1226 sdio0_bus4: sdio0-bus4 {
1227 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1228 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1229 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1230 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1233 sdio0_cmd: sdio0-cmd {
1234 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1237 sdio0_clk: sdio0-clk {
1238 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1241 sdio0_cd: sdio0-cd {
1242 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1245 sdio0_wp: sdio0-wp {
1246 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1249 sdio0_pwr: sdio0-pwr {
1250 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1253 sdio0_bkpwr: sdio0-bkpwr {
1254 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1257 sdio0_int: sdio0-int {
1258 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1263 sdio1_bus1: sdio1-bus1 {
1264 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
1267 sdio1_bus4: sdio1-bus4 {
1268 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
1269 <3 25 RK_FUNC_4 &pcfg_pull_up>,
1270 <3 26 RK_FUNC_4 &pcfg_pull_up>,
1271 <3 27 RK_FUNC_4 &pcfg_pull_up>;
1274 sdio1_cd: sdio1-cd {
1275 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
1278 sdio1_wp: sdio1-wp {
1279 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
1282 sdio1_bkpwr: sdio1-bkpwr {
1283 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
1286 sdio1_int: sdio1-int {
1287 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
1290 sdio1_cmd: sdio1-cmd {
1291 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
1294 sdio1_clk: sdio1-clk {
1295 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
1298 sdio1_pwr: sdio1-pwr {
1299 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
1304 emmc_clk: emmc-clk {
1305 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1308 emmc_cmd: emmc-cmd {
1309 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1312 emmc_pwr: emmc-pwr {
1313 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1316 emmc_bus1: emmc-bus1 {
1317 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1320 emmc_bus4: emmc-bus4 {
1321 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1322 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1323 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1324 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1327 emmc_bus8: emmc-bus8 {
1328 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1329 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1330 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1331 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1332 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1333 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1334 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1335 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1340 spi0_clk: spi0-clk {
1341 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1343 spi0_cs0: spi0-cs0 {
1344 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1347 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1350 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1352 spi0_cs1: spi0-cs1 {
1353 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1357 spi1_clk: spi1-clk {
1358 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1360 spi1_cs0: spi1-cs0 {
1361 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1364 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1367 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1372 spi2_cs1: spi2-cs1 {
1373 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1375 spi2_clk: spi2-clk {
1376 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1378 spi2_cs0: spi2-cs0 {
1379 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1382 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1385 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1390 uart0_xfer: uart0-xfer {
1391 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1392 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1395 uart0_cts: uart0-cts {
1396 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1399 uart0_rts: uart0-rts {
1400 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1405 uart1_xfer: uart1-xfer {
1406 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1407 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1410 uart1_cts: uart1-cts {
1411 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1414 uart1_rts: uart1-rts {
1415 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1420 uart2_xfer: uart2-xfer {
1421 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1422 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1424 /* no rts / cts for uart2 */
1428 uart3_xfer: uart3-xfer {
1429 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1430 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1433 uart3_cts: uart3-cts {
1434 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1437 uart3_rts: uart3-rts {
1438 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1443 uart4_xfer: uart4-xfer {
1444 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1445 <5 13 3 &pcfg_pull_none>;
1448 uart4_cts: uart4-cts {
1449 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1452 uart4_rts: uart4-rts {
1453 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1459 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1464 pwm0_pin: pwm0-pin {
1465 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1470 pwm1_pin: pwm1-pin {
1471 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1476 pwm2_pin: pwm2-pin {
1477 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
1482 pwm3_pin: pwm3-pin {
1483 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
1488 rgmii_pins: rgmii-pins {
1489 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1490 <3 31 3 &pcfg_pull_none>,
1491 <3 26 3 &pcfg_pull_none>,
1492 <3 27 3 &pcfg_pull_none>,
1493 <3 28 3 &pcfg_pull_none_12ma>,
1494 <3 29 3 &pcfg_pull_none_12ma>,
1495 <3 24 3 &pcfg_pull_none_12ma>,
1496 <3 25 3 &pcfg_pull_none_12ma>,
1497 <4 0 3 &pcfg_pull_none>,
1498 <4 5 3 &pcfg_pull_none>,
1499 <4 6 3 &pcfg_pull_none>,
1500 <4 9 3 &pcfg_pull_none_12ma>,
1501 <4 4 3 &pcfg_pull_none_12ma>,
1502 <4 1 3 &pcfg_pull_none>,
1503 <4 3 3 &pcfg_pull_none>;
1506 rmii_pins: rmii-pins {
1507 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1508 <3 31 3 &pcfg_pull_none>,
1509 <3 28 3 &pcfg_pull_none>,
1510 <3 29 3 &pcfg_pull_none>,
1511 <4 0 3 &pcfg_pull_none>,
1512 <4 5 3 &pcfg_pull_none>,
1513 <4 4 3 &pcfg_pull_none>,
1514 <4 1 3 &pcfg_pull_none>,
1515 <4 2 3 &pcfg_pull_none>,
1516 <4 3 3 &pcfg_pull_none>;
1521 spdif_tx: spdif-tx {
1522 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1527 power: power-controller {
1528 compatible = "rockchip,rk3288-power-controller";
1529 #power-domain-cells = <1>;
1530 rockchip,pmu = <&pmu>;
1531 #address-cells = <1>;
1535 reg = <RK3288_PD_GPU>;
1536 clocks = <&cru ACLK_GPU>;
1540 reg = <RK3288_PD_HEVC>;
1541 clocks = <&cru ACLK_HEVC>,
1542 <&cru SCLK_HEVC_CABAC>,
1543 <&cru SCLK_HEVC_CORE>,
1548 reg = <RK3288_PD_VIO>;
1549 clocks = <&cru ACLK_IEP>,
1563 <&cru PCLK_EDP_CTRL>,
1564 <&cru PCLK_HDMI_CTRL>,
1565 <&cru PCLK_LVDS_PHY>,
1566 <&cru PCLK_MIPI_CSI>,
1567 <&cru PCLK_MIPI_DSI0>,
1568 <&cru PCLK_MIPI_DSI1>,
1569 <&cru SCLK_EDP_24M>,
1571 <&cru SCLK_HDMI_CEC>,
1572 <&cru SCLK_HDMI_HDCP>,
1573 <&cru SCLK_ISP_JPE>,
1579 reg = <RK3288_PD_VIDEO>;
1580 clocks = <&cru ACLK_VCODEC>,