1 #include "skeleton.dtsi"
4 model = "Atmel SAMA5D2 family SoC";
5 compatible = "atmel,sama5d2";
15 slow_xtal: slow_xtal {
16 compatible = "fixed-clock";
18 clock-frequency = <0>;
21 main_xtal: main_xtal {
22 compatible = "fixed-clock";
24 clock-frequency = <0>;
29 compatible = "simple-bus";
35 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
36 reg = <0x00400000 0x100000>;
37 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
38 clock-names = "ohci_clk", "hclk", "uhpck";
43 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
44 reg = <0x00500000 0x100000>;
45 clocks = <&utmi>, <&uhphs_clk>;
46 clock-names = "usb_clk", "ehci_clk";
50 sdmmc0: sdio-host@a0000000 {
51 compatible = "atmel,sama5d2-sdhci";
52 reg = <0xa0000000 0x300>;
53 clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
54 clock-names = "hclock", "multclk", "baseclk";
58 sdmmc1: sdio-host@b0000000 {
59 compatible = "atmel,sama5d2-sdhci";
60 reg = <0xb0000000 0x300>;
61 clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
62 clock-names = "hclock", "multclk", "baseclk";
67 compatible = "simple-bus";
73 compatible = "atmel,sama5d2-pmc", "syscon";
74 reg = <0xf0014000 0x160>;
77 #interrupt-cells = <1>;
81 compatible = "atmel,at91sam9x5-clk-main";
87 compatible = "atmel,sama5d3-clk-pll";
91 atmel,clk-input-range = <12000000 12000000>;
92 #atmel,pll-clk-output-range-cells = <4>;
93 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
98 compatible = "atmel,at91sam9x5-clk-plldiv";
103 audio_pll_frac: audiopll_fracck {
104 compatible = "atmel,sama5d2-clk-audio-pll-frac";
109 audio_pll_pad: audiopll_padck {
110 compatible = "atmel,sama5d2-clk-audio-pll-pad";
112 clocks = <&audio_pll_frac>;
115 audio_pll_pmc: audiopll_pmcck {
116 compatible = "atmel,sama5d2-clk-audio-pll-pmc";
118 clocks = <&audio_pll_frac>;
122 compatible = "atmel,at91sam9x5-clk-utmi";
130 compatible = "atmel,at91sam9x5-clk-master";
132 clocks = <&main>, <&plladiv>, <&utmi>;
133 atmel,clk-output-range = <124000000 166000000>;
134 atmel,clk-divisors = <1 2 4 3>;
140 compatible = "atmel,sama5d4-clk-h32mx";
146 compatible = "atmel,at91sam9x5-clk-usb";
148 clocks = <&plladiv>, <&utmi>;
152 compatible = "atmel,at91sam9x5-clk-programmable";
153 #address-cells = <1>;
155 interrupt-parent = <&pmc>;
156 clocks = <&main>, <&plladiv>, <&utmi>, <&mck>;
175 compatible = "atmel,at91rm9200-clk-system";
176 #address-cells = <1>;
229 compatible = "atmel,at91sam9x5-clk-peripheral";
230 #address-cells = <1>;
235 macb0_clk: macb0_clk@5 {
238 atmel,clk-output-range = <0 83000000>;
241 tdes_clk: tdes_clk@11 {
244 atmel,clk-output-range = <0 83000000>;
247 matrix1_clk: matrix1_clk@14 {
252 hsmc_clk: hsmc_clk@17 {
257 pioA_clk: pioA_clk@18 {
260 atmel,clk-output-range = <0 83000000>;
264 flx0_clk: flx0_clk@19 {
267 atmel,clk-output-range = <0 83000000>;
270 flx1_clk: flx1_clk@20 {
273 atmel,clk-output-range = <0 83000000>;
276 flx2_clk: flx2_clk@21 {
279 atmel,clk-output-range = <0 83000000>;
282 flx3_clk: flx3_clk@22 {
285 atmel,clk-output-range = <0 83000000>;
288 flx4_clk: flx4_clk@23 {
291 atmel,clk-output-range = <0 83000000>;
294 uart0_clk: uart0_clk@24 {
297 atmel,clk-output-range = <0 83000000>;
300 uart1_clk: uart1_clk@25 {
303 atmel,clk-output-range = <0 83000000>;
307 uart2_clk: uart2_clk@26 {
310 atmel,clk-output-range = <0 83000000>;
313 uart3_clk: uart3_clk@27 {
316 atmel,clk-output-range = <0 83000000>;
319 uart4_clk: uart4_clk@28 {
322 atmel,clk-output-range = <0 83000000>;
325 twi0_clk: twi0_clk@29 {
328 atmel,clk-output-range = <0 83000000>;
331 twi1_clk: twi1_clk@30 {
334 atmel,clk-output-range = <0 83000000>;
337 spi0_clk: spi0_clk@33 {
340 atmel,clk-output-range = <0 83000000>;
344 spi1_clk: spi1_clk@34 {
347 atmel,clk-output-range = <0 83000000>;
350 tcb0_clk: tcb0_clk@35 {
353 atmel,clk-output-range = <0 83000000>;
356 tcb1_clk: tcb1_clk@36 {
359 atmel,clk-output-range = <0 83000000>;
362 pwm_clk: pwm_clk@38 {
365 atmel,clk-output-range = <0 83000000>;
368 adc_clk: adc_clk@40 {
371 atmel,clk-output-range = <0 83000000>;
374 uhphs_clk: uhphs_clk@41 {
377 atmel,clk-output-range = <0 83000000>;
380 udphs_clk: udphs_clk@42 {
383 atmel,clk-output-range = <0 83000000>;
386 ssc0_clk: ssc0_clk@43 {
389 atmel,clk-output-range = <0 83000000>;
392 ssc1_clk: ssc1_clk@44 {
395 atmel,clk-output-range = <0 83000000>;
398 trng_clk: trng_clk@47 {
401 atmel,clk-output-range = <0 83000000>;
404 pdmic_clk: pdmic_clk@48 {
407 atmel,clk-output-range = <0 83000000>;
410 i2s0_clk: i2s0_clk@54 {
413 atmel,clk-output-range = <0 83000000>;
416 i2s1_clk: i2s1_clk@55 {
419 atmel,clk-output-range = <0 83000000>;
422 can0_clk: can0_clk@56 {
425 atmel,clk-output-range = <0 83000000>;
428 can1_clk: can1_clk@57 {
431 atmel,clk-output-range = <0 83000000>;
434 classd_clk: classd_clk@59 {
437 atmel,clk-output-range = <0 83000000>;
442 compatible = "atmel,at91sam9x5-clk-peripheral";
443 #address-cells = <1>;
448 dma0_clk: dma0_clk@6 {
453 dma1_clk: dma1_clk@7 {
463 aesb_clk: aesb_clk@10 {
468 sha_clk: sha_clk@12 {
473 mpddr_clk: mpddr_clk@13 {
478 matrix0_clk: matrix0_clk@15 {
483 sdmmc0_hclk: sdmmc0_hclk@31 {
489 sdmmc1_hclk: sdmmc1_hclk@32 {
495 lcdc_clk: lcdc_clk@45 {
500 isc_clk: isc_clk@46 {
505 qspi0_clk: qspi0_clk@52 {
510 qspi1_clk: qspi1_clk@53 {
517 compatible = "atmel,sama5d2-clk-generated";
518 #address-cells = <1>;
520 interrupt-parent = <&pmc>;
521 clocks = <&main>, <&plla>, <&utmi>, <&mck>;
524 sdmmc0_gclk: sdmmc0_gclk@31 {
530 sdmmc1_gclk: sdmmc1_gclk@32 {
536 tcb0_gclk: tcb0_gclk@35 {
539 atmel,clk-output-range = <0 83000000>;
542 tcb1_gclk: tcb1_gclk@36 {
545 atmel,clk-output-range = <0 83000000>;
548 pwm_gclk: pwm_gclk@38 {
551 atmel,clk-output-range = <0 83000000>;
554 pdmic_gclk: pdmic_gclk@48 {
559 i2s0_gclk: i2s0_gclk@54 {
564 i2s1_gclk: i2s1_gclk@55 {
569 can0_gclk: can0_gclk@56 {
572 atmel,clk-output-range = <0 80000000>;
575 can1_gclk: can1_gclk@57 {
578 atmel,clk-output-range = <0 80000000>;
581 classd_gclk: classd_gclk@59 {
584 atmel,clk-output-range = <0 100000000>;
589 qspi0: spi@f0020000 {
590 compatible = "atmel,sama5d2-qspi";
591 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
592 reg-names = "qspi_base", "qspi_mmap";
593 #address-cells = <1>;
595 clocks = <&qspi0_clk>;
600 compatible = "atmel,at91rm9200-spi";
601 reg = <0xf8000000 0x100>;
602 clocks = <&spi0_clk>;
603 clock-names = "spi_clk";
604 #address-cells = <1>;
609 macb0: ethernet@f8008000 {
610 compatible = "cdns,macb";
611 reg = <0xf8008000 0x1000>;
612 #address-cells = <1>;
614 clocks = <&macb0_clk>, <&macb0_clk>;
615 clock-names = "hclk", "pclk";
619 uart1: serial@f8020000 {
620 compatible = "atmel,at91sam9260-usart";
621 reg = <0xf8020000 0x100>;
622 clocks = <&uart1_clk>;
623 clock-names = "usart";
628 compatible = "atmel,sama5d2-i2c";
629 reg = <0xf8028000 0x100>;
630 #address-cells = <1>;
632 clocks = <&twi0_clk>;
637 compatible = "atmel,sama5d3-rstc";
638 reg = <0xf8048000 0x10>;
643 compatible = "atmel,sama5d2-shdwc";
644 reg = <0xf8048010 0x10>;
646 #address-cells = <1>;
648 atmel,wakeup-rtc-timer;
651 pit: timer@f8048030 {
652 compatible = "atmel,at91sam9260-pit";
653 reg = <0xf8048030 0x10>;
658 compatible = "atmel,sama5d4-wdt";
659 reg = <0xf8048040 0x10>;
665 compatible = "atmel,sama5d2-sfr", "syscon";
666 reg = <0xf8030000 0x98>;
670 compatible = "atmel,at91sam9x5-sckc";
671 reg = <0xf8048050 0x4>;
673 slow_rc_osc: slow_rc_osc {
674 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
676 clock-frequency = <32768>;
677 clock-accuracy = <250000000>;
678 atmel,startup-time-usec = <75>;
682 compatible = "atmel,at91sam9x5-clk-slow-osc";
684 clocks = <&slow_xtal>;
685 atmel,startup-time-usec = <1200000>;
689 compatible = "atmel,at91sam9x5-clk-slow";
691 clocks = <&slow_rc_osc &slow_osc>;
696 compatible = "atmel,at91rm9200-spi";
697 reg = <0xfc000000 0x100>;
698 #address-cells = <1>;
704 compatible = "atmel,sama5d2-i2c";
705 reg = <0xfc028000 0x100>;
706 #address-cells = <1>;
708 clocks = <&twi1_clk>;
712 pioA: gpio@fc038000 {
713 compatible = "atmel,sama5d2-gpio";
714 reg = <0xfc038000 0x600>;
715 clocks = <&pioA_clk>;
721 compatible = "atmel,sama5d2-pinctrl";