2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "skeleton.dtsi"
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/pinctrl/sun4i-a10.h>
49 interrupt-parent = <&gic>;
56 compatible = "arm,cortex-a7";
62 compatible = "arm,cortex-a7";
68 compatible = "arm,cortex-a7";
74 compatible = "arm,cortex-a7";
81 compatible = "arm,armv7-timer";
82 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
83 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
84 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
85 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
86 clock-frequency = <24000000>;
87 arm,cpu-registers-not-fw-configured;
91 reg = <0x40000000 0x80000000>;
101 compatible = "fixed-clock";
102 clock-frequency = <24000000>;
103 clock-output-names = "osc24M";
108 compatible = "fixed-clock";
109 clock-frequency = <32768>;
110 clock-output-names = "osc32k";
115 compatible = "allwinner,sun8i-a23-pll1-clk";
116 reg = <0x01c20000 0x4>;
118 clock-output-names = "pll1";
121 /* dummy clock until actually implemented */
124 compatible = "fixed-clock";
125 clock-frequency = <0>;
126 clock-output-names = "pll5";
131 compatible = "allwinner,sun6i-a31-pll6-clk";
132 reg = <0x01c20028 0x4>;
134 clock-output-names = "pll6", "pll6x2", "pll6d2";
139 compatible = "allwinner,sun6i-a31-pll6-clk";
140 reg = <0x01c20044 0x4>;
142 clock-output-names = "pll8", "pll8x2";
145 cpu: cpu_clk@01c20050 {
147 compatible = "allwinner,sun4i-a10-cpu-clk";
148 reg = <0x01c20050 0x4>;
149 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
150 clock-output-names = "cpu";
153 axi: axi_clk@01c20050 {
155 compatible = "allwinner,sun4i-a10-axi-clk";
156 reg = <0x01c20050 0x4>;
158 clock-output-names = "axi";
161 ahb1: ahb1_clk@01c20054 {
163 compatible = "allwinner,sun6i-a31-ahb1-clk";
164 reg = <0x01c20054 0x4>;
165 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
166 clock-output-names = "ahb1";
169 ahb2: ahb2_clk@01c2005c {
171 compatible = "allwinner,sun8i-h3-ahb2-clk";
172 reg = <0x01c2005c 0x4>;
173 clocks = <&ahb1>, <&pll6 2>;
174 clock-output-names = "ahb2";
177 apb1: apb1_clk@01c20054 {
179 compatible = "allwinner,sun4i-a10-apb0-clk";
180 reg = <0x01c20054 0x4>;
182 clock-output-names = "apb1";
185 apb2: apb2_clk@01c20058 {
187 compatible = "allwinner,sun4i-a10-apb1-clk";
188 reg = <0x01c20058 0x4>;
189 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
190 clock-output-names = "apb2";
193 bus_gates: clk@01c20060 {
195 compatible = "allwinner,sun8i-h3-bus-gates-clk";
196 reg = <0x01c20060 0x14>;
197 clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
198 clock-names = "ahb1", "ahb2", "apb1", "apb2";
199 clock-indices = <5>, <6>, <8>,
218 clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0",
219 "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand",
220 "ahb1_sdram", "ahb2_gmac", "ahb1_ts",
221 "ahb1_hstimer", "ahb1_spi0",
222 "ahb1_spi1", "ahb1_otg",
223 "ahb1_otg_ehci0", "ahb1_ehic1",
224 "ahb1_ehic2", "ahb1_ehic3",
225 "ahb1_otg_ohci0", "ahb2_ohic1",
226 "ahb2_ohic2", "ahb2_ohic3", "ahb1_ve",
227 "ahb1_lcd0", "ahb1_lcd1", "ahb1_deint",
228 "ahb1_csi", "ahb1_tve", "ahb1_hdmi",
229 "ahb1_de", "ahb1_gpu", "ahb1_msgbox",
230 "ahb1_spinlock", "apb1_codec",
231 "apb1_spdif", "apb1_pio", "apb1_ths",
232 "apb1_i2s0", "apb1_i2s1", "apb1_i2s2",
233 "apb2_i2c0", "apb2_i2c1", "apb2_i2c2",
234 "apb2_uart0", "apb2_uart1",
235 "apb2_uart2", "apb2_uart3", "apb2_scr",
236 "ahb1_ephy", "ahb1_dbg";
239 mmc0_clk: clk@01c20088 {
241 compatible = "allwinner,sun4i-a10-mmc-clk";
242 reg = <0x01c20088 0x4>;
243 clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
244 clock-output-names = "mmc0",
249 mmc1_clk: clk@01c2008c {
251 compatible = "allwinner,sun4i-a10-mmc-clk";
252 reg = <0x01c2008c 0x4>;
253 clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
254 clock-output-names = "mmc1",
259 mmc2_clk: clk@01c20090 {
261 compatible = "allwinner,sun4i-a10-mmc-clk";
262 reg = <0x01c20090 0x4>;
263 clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
264 clock-output-names = "mmc2",
269 usb_clk: clk@01c200cc {
272 compatible = "allwinner,sun8i-h3-usb-clk";
273 reg = <0x01c200cc 0x4>;
275 clock-output-names = "usb_phy0", "usb_phy1",
276 "usb_phy2", "usb_phy3",
277 "usb_ohci0", "usb_ohci1",
278 "usb_ohci2", "usb_ohci3";
281 mbus_clk: clk@01c2015c {
283 compatible = "allwinner,sun8i-a23-mbus-clk";
284 reg = <0x01c2015c 0x4>;
285 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
286 clock-output-names = "mbus";
291 compatible = "simple-bus";
292 #address-cells = <1>;
296 dma: dma-controller@01c02000 {
297 compatible = "allwinner,sun8i-h3-dma";
298 reg = <0x01c02000 0x1000>;
299 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&bus_gates 6>;
301 resets = <&bus_rst 6>;
306 compatible = "allwinner,sun5i-a13-mmc";
307 reg = <0x01c0f000 0x1000>;
308 clocks = <&bus_gates 8>,
316 resets = <&bus_rst 8>;
318 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
320 #address-cells = <1>;
325 compatible = "allwinner,sun5i-a13-mmc";
326 reg = <0x01c10000 0x1000>;
327 clocks = <&bus_gates 9>,
335 resets = <&bus_rst 9>;
337 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
339 #address-cells = <1>;
344 compatible = "allwinner,sun5i-a13-mmc";
345 reg = <0x01c11000 0x1000>;
346 clocks = <&bus_gates 10>,
354 resets = <&bus_rst 10>;
356 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
358 #address-cells = <1>;
362 usbphy: phy@01c19400 {
363 compatible = "allwinner,sun8i-h3-usb-phy";
364 reg = <0x01c19400 0x2c>,
369 reg-names = "phy_ctrl",
374 clocks = <&usb_clk 8>,
378 clock-names = "usb0_phy",
382 resets = <&usb_clk 0>,
386 reset-names = "usb0_reset",
394 ehci1: usb@01c1b000 {
395 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
396 reg = <0x01c1b000 0x100>;
397 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&bus_gates 25>, <&bus_gates 29>;
399 resets = <&bus_rst 25>, <&bus_rst 29>;
405 ohci1: usb@01c1b400 {
406 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
407 reg = <0x01c1b400 0x100>;
408 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&bus_gates 29>, <&bus_gates 25>,
411 resets = <&bus_rst 29>, <&bus_rst 25>;
417 ehci2: usb@01c1c000 {
418 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
419 reg = <0x01c1c000 0x100>;
420 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&bus_gates 26>, <&bus_gates 30>;
422 resets = <&bus_rst 26>, <&bus_rst 30>;
428 ohci2: usb@01c1c400 {
429 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
430 reg = <0x01c1c400 0x100>;
431 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&bus_gates 30>, <&bus_gates 26>,
434 resets = <&bus_rst 30>, <&bus_rst 26>;
440 ehci3: usb@01c1d000 {
441 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
442 reg = <0x01c1d000 0x100>;
443 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&bus_gates 27>, <&bus_gates 31>;
445 resets = <&bus_rst 27>, <&bus_rst 31>;
451 ohci3: usb@01c1d400 {
452 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
453 reg = <0x01c1d400 0x100>;
454 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&bus_gates 31>, <&bus_gates 27>,
457 resets = <&bus_rst 31>, <&bus_rst 27>;
463 pio: pinctrl@01c20800 {
464 compatible = "allwinner,sun8i-h3-pinctrl";
465 reg = <0x01c20800 0x400>;
466 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&bus_gates 69>;
471 interrupt-controller;
472 #interrupt-cells = <2>;
474 uart0_pins_a: uart0@0 {
475 allwinner,pins = "PA4", "PA5";
476 allwinner,function = "uart0";
477 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
478 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
481 mmc0_pins_a: mmc0@0 {
482 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
484 allwinner,function = "mmc0";
485 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
486 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
489 mmc0_cd_pin: mmc0_cd_pin@0 {
490 allwinner,pins = "PF6";
491 allwinner,function = "gpio_in";
492 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
493 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
496 mmc1_pins_a: mmc1@0 {
497 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
499 allwinner,function = "mmc1";
500 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
501 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
505 bus_rst: reset@01c202c0 {
507 compatible = "allwinner,sun8i-h3-bus-reset";
508 reg = <0x01c202c0 0x1c>;
512 compatible = "allwinner,sun4i-a10-timer";
513 reg = <0x01c20c00 0xa0>;
514 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
519 wdt0: watchdog@01c20ca0 {
520 compatible = "allwinner,sun6i-a31-wdt";
521 reg = <0x01c20ca0 0x20>;
522 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
525 uart0: serial@01c28000 {
526 compatible = "snps,dw-apb-uart";
527 reg = <0x01c28000 0x400>;
528 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&bus_gates 112>;
532 resets = <&bus_rst 144>;
533 dmas = <&dma 6>, <&dma 6>;
534 dma-names = "rx", "tx";
538 uart1: serial@01c28400 {
539 compatible = "snps,dw-apb-uart";
540 reg = <0x01c28400 0x400>;
541 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&bus_gates 113>;
545 resets = <&bus_rst 145>;
546 dmas = <&dma 7>, <&dma 7>;
547 dma-names = "rx", "tx";
551 uart2: serial@01c28800 {
552 compatible = "snps,dw-apb-uart";
553 reg = <0x01c28800 0x400>;
554 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&bus_gates 114>;
558 resets = <&bus_rst 146>;
559 dmas = <&dma 8>, <&dma 8>;
560 dma-names = "rx", "tx";
564 uart3: serial@01c28c00 {
565 compatible = "snps,dw-apb-uart";
566 reg = <0x01c28c00 0x400>;
567 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&bus_gates 115>;
571 resets = <&bus_rst 147>;
572 dmas = <&dma 9>, <&dma 9>;
573 dma-names = "rx", "tx";
577 gic: interrupt-controller@01c81000 {
578 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
579 reg = <0x01c81000 0x1000>,
583 interrupt-controller;
584 #interrupt-cells = <3>;
585 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
589 compatible = "allwinner,sun6i-a31-rtc";
590 reg = <0x01f00000 0x54>;
591 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;