1 #include <dt-bindings/clock/tegra20-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include "skeleton.dtsi"
8 compatible = "nvidia,tegra20";
9 interrupt-parent = <&intc>;
12 compatible = "nvidia,tegra20-host1x", "simple-bus";
13 reg = <0x50000000 0x00024000>;
14 interrupts = <0 65 0x04 /* mpcore syncpt */
15 0 67 0x04>; /* mpcore general */
21 ranges = <0x54000000 0x54000000 0x04000000>;
23 /* video-encoding/decoding */
25 reg = <0x54040000 0x00040000>;
26 interrupts = <0 68 0x04>;
32 reg = <0x54080000 0x00040000>;
33 interrupts = <0 69 0x04>;
39 reg = <0x540c0000 0x00040000>;
40 interrupts = <0 70 0x04>;
46 reg = <0x54100000 0x00040000>;
47 interrupts = <0 71 0x04>;
53 reg = <0x54140000 0x00040000>;
54 interrupts = <0 72 0x04>;
60 reg = <0x54180000 0x00040000>;
64 /* display controllers */
66 compatible = "nvidia,tegra20-dc";
67 reg = <0x54200000 0x00040000>;
68 interrupts = <0 73 0x04>;
77 compatible = "nvidia,tegra20-dc";
78 reg = <0x54240000 0x00040000>;
79 interrupts = <0 74 0x04>;
89 compatible = "nvidia,tegra20-hdmi";
90 reg = <0x54280000 0x00040000>;
91 interrupts = <0 75 0x04>;
96 compatible = "nvidia,tegra20-tvo";
97 reg = <0x542c0000 0x00040000>;
98 interrupts = <0 76 0x04>;
103 compatible = "nvidia,tegra20-dsi";
104 reg = <0x54300000 0x00040000>;
109 intc: interrupt-controller@50041000 {
110 compatible = "nvidia,tegra20-gic";
111 interrupt-controller;
112 #interrupt-cells = <1>;
113 reg = < 0x50041000 0x1000 >,
114 < 0x50040100 0x0100 >;
117 tegra_car: clock@60006000 {
118 compatible = "nvidia,tegra20-car";
119 reg = <0x60006000 0x1000>;
124 compatible = "nvidia,tegra20-apbdma";
125 reg = <0x6000a000 0x1200>;
126 interrupts = <0 104 0x04
144 gpio: gpio@6000d000 {
145 compatible = "nvidia,tegra20-gpio";
146 reg = <0x6000d000 0x1000>;
147 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
156 #interrupt-cells = <2>;
157 interrupt-controller;
160 pinmux: pinmux@70000000 {
161 compatible = "nvidia,tegra20-pinmux";
162 reg = < 0x70000014 0x10 /* Tri-state registers */
163 0x70000080 0x20 /* Mux registers */
164 0x700000a0 0x14 /* Pull-up/down registers */
165 0x70000868 0xa8 >; /* Pad control registers */
169 #address-cells = <1>;
171 compatible = "nvidia,tegra20-das";
172 reg = <0x70000c00 0x80>;
176 #address-cells = <1>;
178 compatible = "nvidia,tegra20-i2s";
179 reg = <0x70002800 0x200>;
185 #address-cells = <1>;
187 compatible = "nvidia,tegra20-i2s";
188 reg = <0x70002a00 0x200>;
193 uarta: serial@70006000 {
194 compatible = "nvidia,tegra20-uart";
195 reg = <0x70006000 0x40>;
197 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
199 resets = <&tegra_car 6>;
200 reset-names = "serial";
201 dmas = <&apbdma 8>, <&apbdma 8>;
202 dma-names = "rx", "tx";
206 uartb: serial@70006040 {
207 compatible = "nvidia,tegra20-uart";
208 reg = <0x70006040 0x40>;
210 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
212 resets = <&tegra_car 7>;
213 reset-names = "serial";
214 dmas = <&apbdma 9>, <&apbdma 9>;
215 dma-names = "rx", "tx";
219 uartc: serial@70006200 {
220 compatible = "nvidia,tegra20-uart";
221 reg = <0x70006200 0x100>;
223 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
225 resets = <&tegra_car 55>;
226 reset-names = "serial";
227 dmas = <&apbdma 10>, <&apbdma 10>;
228 dma-names = "rx", "tx";
232 uartd: serial@70006300 {
233 compatible = "nvidia,tegra20-uart";
234 reg = <0x70006300 0x100>;
236 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
238 resets = <&tegra_car 65>;
239 reset-names = "serial";
240 dmas = <&apbdma 19>, <&apbdma 19>;
241 dma-names = "rx", "tx";
245 uarte: serial@70006400 {
246 compatible = "nvidia,tegra20-uart";
247 reg = <0x70006400 0x100>;
249 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
251 resets = <&tegra_car 66>;
252 reset-names = "serial";
253 dmas = <&apbdma 20>, <&apbdma 20>;
254 dma-names = "rx", "tx";
258 nand: nand-controller@70008000 {
259 #address-cells = <1>;
261 compatible = "nvidia,tegra20-nand";
262 reg = <0x70008000 0x100>;
266 compatible = "nvidia,tegra20-pwm";
267 reg = <0x7000a000 0x100>;
272 #address-cells = <1>;
274 compatible = "nvidia,tegra20-i2c";
275 reg = <0x7000C000 0x100>;
277 /* PERIPH_ID_I2C1, PLL_P_OUT3 */
278 clocks = <&tegra_car 12>, <&tegra_car 124>;
282 compatible = "nvidia,tegra20-sflash";
283 reg = <0x7000c380 0x80>;
284 interrupts = <0 39 0x04>;
285 nvidia,dma-request-selector = <&apbdma 11>;
286 #address-cells = <1>;
289 /* PERIPH_ID_SPI1, PLLP_OUT0 */
290 clocks = <&tegra_car 43>;
294 #address-cells = <1>;
296 compatible = "nvidia,tegra20-i2c";
297 reg = <0x7000C400 0x100>;
298 interrupts = < 116 >;
299 /* PERIPH_ID_I2C2, PLL_P_OUT3 */
300 clocks = <&tegra_car 54>, <&tegra_car 124>;
304 #address-cells = <1>;
306 compatible = "nvidia,tegra20-i2c";
307 reg = <0x7000C500 0x100>;
308 interrupts = < 124 >;
309 /* PERIPH_ID_I2C3, PLL_P_OUT3 */
310 clocks = <&tegra_car 67>, <&tegra_car 124>;
314 #address-cells = <1>;
316 compatible = "nvidia,tegra20-i2c-dvc";
317 reg = <0x7000D000 0x200>;
319 /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
320 clocks = <&tegra_car 47>, <&tegra_car 124>;
324 compatible = "nvidia,tegra20-slink";
325 reg = <0x7000d400 0x200>;
326 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
327 #address-cells = <1>;
329 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
330 resets = <&tegra_car 41>;
332 dmas = <&apbdma 15>, <&apbdma 15>;
333 dma-names = "rx", "tx";
338 compatible = "nvidia,tegra20-slink";
339 reg = <0x7000d600 0x200>;
340 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
341 #address-cells = <1>;
343 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
344 resets = <&tegra_car 44>;
346 dmas = <&apbdma 16>, <&apbdma 16>;
347 dma-names = "rx", "tx";
352 compatible = "nvidia,tegra20-slink";
353 reg = <0x7000d800 0x200>;
354 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
355 #address-cells = <1>;
357 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
358 resets = <&tegra_car 46>;
360 dmas = <&apbdma 17>, <&apbdma 17>;
361 dma-names = "rx", "tx";
366 compatible = "nvidia,tegra20-slink";
367 reg = <0x7000da00 0x200>;
368 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
369 #address-cells = <1>;
371 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
372 resets = <&tegra_car 68>;
374 dmas = <&apbdma 18>, <&apbdma 18>;
375 dma-names = "rx", "tx";
381 compatible = "nvidia,tegra20-kbc";
382 reg = <0x7000e200 0x0078>;
386 #address-cells = < 1 >;
388 compatible = "nvidia,tegra20-emc";
389 reg = <0x7000f400 0x200>;
392 pcie-controller@80003000 {
393 compatible = "nvidia,tegra20-pcie";
395 reg = <0x80003000 0x00000800 /* PADS registers */
396 0x80003800 0x00000200 /* AFI registers */
397 0x90000000 0x10000000>; /* configuration space */
398 reg-names = "pads", "afi", "cs";
399 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
400 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
401 interrupt-names = "intr", "msi";
403 #interrupt-cells = <1>;
404 interrupt-map-mask = <0 0 0 0>;
405 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
407 bus-range = <0x00 0xff>;
408 #address-cells = <3>;
411 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
412 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
413 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
414 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
415 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
417 clocks = <&tegra_car TEGRA20_CLK_PEX>,
418 <&tegra_car TEGRA20_CLK_AFI>,
419 <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
420 <&tegra_car TEGRA20_CLK_PLL_E>;
421 clock-names = "pex", "afi", "pcie_xclk", "pll_e";
426 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
427 reg = <0x000800 0 0 0 0>;
430 #address-cells = <3>;
434 nvidia,num-lanes = <2>;
439 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
440 reg = <0x001000 0 0 0 0>;
443 #address-cells = <3>;
447 nvidia,num-lanes = <2>;
452 compatible = "nvidia,tegra20-ehci", "usb-ehci";
453 reg = <0xc5000000 0x4000>;
456 clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
457 nvidia,has-legacy-mode;
461 compatible = "nvidia,tegra20-ehci", "usb-ehci";
462 reg = <0xc5004000 0x4000>;
465 clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
469 compatible = "nvidia,tegra20-ehci", "usb-ehci";
470 reg = <0xc5008000 0x4000>;
471 interrupts = < 129 >;
473 clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
477 compatible = "nvidia,tegra20-sdhci";
478 reg = <0xc8000000 0x200>;
479 interrupts = <0 14 0x04>;
480 clocks = <&tegra_car 14>;
485 compatible = "nvidia,tegra20-sdhci";
486 reg = <0xc8000200 0x200>;
487 interrupts = <0 15 0x04>;
488 clocks = <&tegra_car 9>;
493 compatible = "nvidia,tegra20-sdhci";
494 reg = <0xc8000400 0x200>;
495 interrupts = <0 19 0x04>;
496 clocks = <&tegra_car 69>;
501 compatible = "nvidia,tegra20-sdhci";
502 reg = <0xc8000600 0x200>;
503 interrupts = <0 31 0x04>;
504 clocks = <&tegra_car 15>;