git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-ph1-pro5.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-Pro5 SoC
   3  *
   4  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 /include/ "uniphier-common32.dtsi"
  10
  11 / {
  12         compatible = "socionext,ph1-pro5";
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17                 enable-method = "socionext,uniphier-smp";
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         next-level-cache = <&l2>;
  24                 };
  25
  26                 cpu@1 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a9";
  29                         reg = <1>;
  30                         next-level-cache = <&l2>;
  31                 };
  32         };
  33
  34         clocks {
  35                 arm_timer_clk: arm_timer_clk {
  36                         #clock-cells = <0>;
  37                         compatible = "fixed-clock";
  38                         clock-frequency = <50000000>;
  39                 };
  40
  41                 uart_clk: uart_clk {
  42                         #clock-cells = <0>;
  43                         compatible = "fixed-clock";
  44                         clock-frequency = <73728000>;
  45                 };
  46
  47                 i2c_clk: i2c_clk {
  48                         #clock-cells = <0>;
  49                         compatible = "fixed-clock";
  50                         clock-frequency = <50000000>;
  51                 };
  52         };
  53 };
  54
  55 &soc {
  56         l2: l2-cache@500c0000 {
  57                 compatible = "socionext,uniphier-system-cache";
  58                 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
  59                 interrupts = <0 190 4>, <0 191 4>;
  60                 cache-unified;
  61                 cache-size = <(2 * 1024 * 1024)>;
  62                 cache-sets = <512>;
  63                 cache-line-size = <128>;
  64                 cache-level = <2>;
  65                 next-level-cache = <&l3>;
  66         };
  67
  68         l3: l3-cache@500c8000 {
  69                 compatible = "socionext,uniphier-system-cache";
  70                 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
  71                 interrupts = <0 174 4>, <0 175 4>;
  72                 cache-unified;
  73                 cache-size = <(2 * 1024 * 1024)>;
  74                 cache-sets = <512>;
  75                 cache-line-size = <256>;
  76                 cache-level = <3>;
  77         };
  78
  79         i2c0: i2c@58780000 {
  80                 compatible = "socionext,uniphier-fi2c";
  81                 status = "disabled";
  82                 reg = <0x58780000 0x80>;
  83                 #address-cells = <1>;
  84                 #size-cells = <0>;
  85                 interrupts = <0 41 4>;
  86                 pinctrl-names = "default";
  87                 pinctrl-0 = <&pinctrl_i2c0>;
  88                 clocks = <&i2c_clk>;
  89                 clock-frequency = <100000>;
  90         };
  91
  92         i2c1: i2c@58781000 {
  93                 compatible = "socionext,uniphier-fi2c";
  94                 status = "disabled";
  95                 reg = <0x58781000 0x80>;
  96                 #address-cells = <1>;
  97                 #size-cells = <0>;
  98                 interrupts = <0 42 4>;
  99                 pinctrl-names = "default";
 100                 pinctrl-0 = <&pinctrl_i2c1>;
 101                 clocks = <&i2c_clk>;
 102                 clock-frequency = <100000>;
 103         };
 104
 105         i2c2: i2c@58782000 {
 106                 compatible = "socionext,uniphier-fi2c";
 107                 status = "disabled";
 108                 reg = <0x58782000 0x80>;
 109                 #address-cells = <1>;
 110                 #size-cells = <0>;
 111                 interrupts = <0 43 4>;
 112                 pinctrl-names = "default";
 113                 pinctrl-0 = <&pinctrl_i2c2>;
 114                 clocks = <&i2c_clk>;
 115                 clock-frequency = <100000>;
 116         };
 117
 118         i2c3: i2c@58783000 {
 119                 compatible = "socionext,uniphier-fi2c";
 120                 status = "disabled";
 121                 reg = <0x58783000 0x80>;
 122                 #address-cells = <1>;
 123                 #size-cells = <0>;
 124                 interrupts = <0 44 4>;
 125                 pinctrl-names = "default";
 126                 pinctrl-0 = <&pinctrl_i2c3>;
 127                 clocks = <&i2c_clk>;
 128                 clock-frequency = <100000>;
 129         };
 130
 131         /* i2c4 does not exist */
 132
 133         /* chip-internal connection for DMD */
 134         i2c5: i2c@58785000 {
 135                 compatible = "socionext,uniphier-fi2c";
 136                 reg = <0x58785000 0x80>;
 137                 #address-cells = <1>;
 138                 #size-cells = <0>;
 139                 interrupts = <0 25 4>;
 140                 clocks = <&i2c_clk>;
 141                 clock-frequency = <400000>;
 142         };
 143
 144         /* chip-internal connection for HDMI */
 145         i2c6: i2c@58786000 {
 146                 compatible = "socionext,uniphier-fi2c";
 147                 reg = <0x58786000 0x80>;
 148                 #address-cells = <1>;
 149                 #size-cells = <0>;
 150                 interrupts = <0 26 4>;
 151                 clocks = <&i2c_clk>;
 152                 clock-frequency = <400000>;
 153         };
 154
 155         usb0: usb@65a00000 {
 156                 compatible = "socionext,uniphier-xhci", "generic-xhci";
 157                 status = "disabled";
 158                 reg = <0x65a00000 0x100>;
 159                 interrupts = <0 134 4>;
 160                 pinctrl-names = "default";
 161                 pinctrl-0 = <&pinctrl_usb0>;
 162         };
 163
 164         usb1: usb@65c00000 {
 165                 compatible = "socionext,uniphier-xhci", "generic-xhci";
 166                 status = "disabled";
 167                 reg = <0x65c00000 0x100>;
 168                 interrupts = <0 137 4>;
 169                 pinctrl-names = "default";
 170                 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
 171         };
 172 };
 173
 174 &refclk {
 175         clock-frequency = <20000000>;
 176 };
 177
 178 &serial0 {
 179         clock-frequency = <73728000>;
 180 };
 181
 182 &serial1 {
 183         clock-frequency = <73728000>;
 184 };
 185
 186 &serial2 {
 187         clock-frequency = <73728000>;
 188 };
 189
 190 &serial3 {
 191         clock-frequency = <73728000>;
 192 };
 193
 194 &mio {
 195         compatible = "socionext,ph1-pro5-mioctrl";
 196         clock-names = "stdmac";
 197         clocks = <&sysctrl 10>;
 198 };
 199
 200 &peri {
 201         compatible = "socionext,ph1-pro5-perictrl";
 202         clock-names = "uart", "fi2c";
 203         clocks = <&sysctrl 3>, <&sysctrl 4>;
 204 };
 205
 206 &pinctrl {
 207         compatible = "socionext,ph1-pro5-pinctrl", "syscon";
 208 };
 209
 210 &sysctrl {
 211         compatible = "socionext,ph1-pro5-sysctrl";
 212 };