git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-pxs2.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PXs2 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   8  */
   9
  10 / {
  11         compatible = "socionext,uniphier-pxs2";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         clocks = <&sys_clk 32>;
  24                         enable-method = "psci";
  25                         next-level-cache = <&l2>;
  26                         operating-points-v2 = <&cpu_opp>;
  27                 };
  28
  29                 cpu@1 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a9";
  32                         reg = <1>;
  33                         clocks = <&sys_clk 32>;
  34                         enable-method = "psci";
  35                         next-level-cache = <&l2>;
  36                         operating-points-v2 = <&cpu_opp>;
  37                 };
  38
  39                 cpu@2 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a9";
  42                         reg = <2>;
  43                         clocks = <&sys_clk 32>;
  44                         enable-method = "psci";
  45                         next-level-cache = <&l2>;
  46                         operating-points-v2 = <&cpu_opp>;
  47                 };
  48
  49                 cpu@3 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a9";
  52                         reg = <3>;
  53                         clocks = <&sys_clk 32>;
  54                         enable-method = "psci";
  55                         next-level-cache = <&l2>;
  56                         operating-points-v2 = <&cpu_opp>;
  57                 };
  58         };
  59
  60         cpu_opp: opp_table {
  61                 compatible = "operating-points-v2";
  62                 opp-shared;
  63
  64                 opp-100000000 {
  65                         opp-hz = /bits/ 64 <100000000>;
  66                         clock-latency-ns = <300>;
  67                 };
  68                 opp-150000000 {
  69                         opp-hz = /bits/ 64 <150000000>;
  70                         clock-latency-ns = <300>;
  71                 };
  72                 opp-200000000 {
  73                         opp-hz = /bits/ 64 <200000000>;
  74                         clock-latency-ns = <300>;
  75                 };
  76                 opp-300000000 {
  77                         opp-hz = /bits/ 64 <300000000>;
  78                         clock-latency-ns = <300>;
  79                 };
  80                 opp-400000000 {
  81                         opp-hz = /bits/ 64 <400000000>;
  82                         clock-latency-ns = <300>;
  83                 };
  84                 opp-600000000 {
  85                         opp-hz = /bits/ 64 <600000000>;
  86                         clock-latency-ns = <300>;
  87                 };
  88                 opp-800000000 {
  89                         opp-hz = /bits/ 64 <800000000>;
  90                         clock-latency-ns = <300>;
  91                 };
  92                 opp-1200000000 {
  93                         opp-hz = /bits/ 64 <1200000000>;
  94                         clock-latency-ns = <300>;
  95                 };
  96         };
  97
  98         psci {
  99                 compatible = "arm,psci-0.2";
 100                 method = "smc";
 101         };
 102
 103         clocks {
 104                 refclk: ref {
 105                         compatible = "fixed-clock";
 106                         #clock-cells = <0>;
 107                         clock-frequency = <25000000>;
 108                 };
 109
 110                 arm_timer_clk: arm_timer_clk {
 111                         #clock-cells = <0>;
 112                         compatible = "fixed-clock";
 113                         clock-frequency = <50000000>;
 114                 };
 115         };
 116
 117         soc {
 118                 compatible = "simple-bus";
 119                 #address-cells = <1>;
 120                 #size-cells = <1>;
 121                 ranges;
 122                 interrupt-parent = <&intc>;
 123                 u-boot,dm-pre-reloc;
 124
 125                 l2: l2-cache@500c0000 {
 126                         compatible = "socionext,uniphier-system-cache";
 127                         reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
 128                               <0x506c0000 0x400>;
 129                         interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
 130                         cache-unified;
 131                         cache-size = <(1280 * 1024)>;
 132                         cache-sets = <512>;
 133                         cache-line-size = <128>;
 134                         cache-level = <2>;
 135                 };
 136
 137                 serial0: serial@54006800 {
 138                         compatible = "socionext,uniphier-uart";
 139                         status = "disabled";
 140                         reg = <0x54006800 0x40>;
 141                         interrupts = <0 33 4>;
 142                         pinctrl-names = "default";
 143                         pinctrl-0 = <&pinctrl_uart0>;
 144                         clocks = <&peri_clk 0>;
 145                         clock-frequency = <88900000>;
 146                 };
 147
 148                 serial1: serial@54006900 {
 149                         compatible = "socionext,uniphier-uart";
 150                         status = "disabled";
 151                         reg = <0x54006900 0x40>;
 152                         interrupts = <0 35 4>;
 153                         pinctrl-names = "default";
 154                         pinctrl-0 = <&pinctrl_uart1>;
 155                         clocks = <&peri_clk 1>;
 156                         clock-frequency = <88900000>;
 157                 };
 158
 159                 serial2: serial@54006a00 {
 160                         compatible = "socionext,uniphier-uart";
 161                         status = "disabled";
 162                         reg = <0x54006a00 0x40>;
 163                         interrupts = <0 37 4>;
 164                         pinctrl-names = "default";
 165                         pinctrl-0 = <&pinctrl_uart2>;
 166                         clocks = <&peri_clk 2>;
 167                         clock-frequency = <88900000>;
 168                 };
 169
 170                 serial3: serial@54006b00 {
 171                         compatible = "socionext,uniphier-uart";
 172                         status = "disabled";
 173                         reg = <0x54006b00 0x40>;
 174                         interrupts = <0 177 4>;
 175                         pinctrl-names = "default";
 176                         pinctrl-0 = <&pinctrl_uart3>;
 177                         clocks = <&peri_clk 3>;
 178                         clock-frequency = <88900000>;
 179                 };
 180
 181                 gpio: gpio@55000000 {
 182                         compatible = "socionext,uniphier-gpio";
 183                         reg = <0x55000000 0x200>;
 184                         interrupt-parent = <&aidet>;
 185                         interrupt-controller;
 186                         #interrupt-cells = <2>;
 187                         gpio-controller;
 188                         #gpio-cells = <2>;
 189                         gpio-ranges = <&pinctrl 0 0 0>,
 190                                       <&pinctrl 96 0 0>;
 191                         gpio-ranges-group-names = "gpio_range0",
 192                                                   "gpio_range1";
 193                         ngpios = <232>;
 194                 };
 195
 196                 i2c0: i2c@58780000 {
 197                         compatible = "socionext,uniphier-fi2c";
 198                         status = "disabled";
 199                         reg = <0x58780000 0x80>;
 200                         #address-cells = <1>;
 201                         #size-cells = <0>;
 202                         interrupts = <0 41 4>;
 203                         pinctrl-names = "default";
 204                         pinctrl-0 = <&pinctrl_i2c0>;
 205                         clocks = <&peri_clk 4>;
 206                         clock-frequency = <100000>;
 207                 };
 208
 209                 i2c1: i2c@58781000 {
 210                         compatible = "socionext,uniphier-fi2c";
 211                         status = "disabled";
 212                         reg = <0x58781000 0x80>;
 213                         #address-cells = <1>;
 214                         #size-cells = <0>;
 215                         interrupts = <0 42 4>;
 216                         pinctrl-names = "default";
 217                         pinctrl-0 = <&pinctrl_i2c1>;
 218                         clocks = <&peri_clk 5>;
 219                         clock-frequency = <100000>;
 220                 };
 221
 222                 i2c2: i2c@58782000 {
 223                         compatible = "socionext,uniphier-fi2c";
 224                         status = "disabled";
 225                         reg = <0x58782000 0x80>;
 226                         #address-cells = <1>;
 227                         #size-cells = <0>;
 228                         interrupts = <0 43 4>;
 229                         pinctrl-names = "default";
 230                         pinctrl-0 = <&pinctrl_i2c2>;
 231                         clocks = <&peri_clk 6>;
 232                         clock-frequency = <100000>;
 233                 };
 234
 235                 i2c3: i2c@58783000 {
 236                         compatible = "socionext,uniphier-fi2c";
 237                         status = "disabled";
 238                         reg = <0x58783000 0x80>;
 239                         #address-cells = <1>;
 240                         #size-cells = <0>;
 241                         interrupts = <0 44 4>;
 242                         pinctrl-names = "default";
 243                         pinctrl-0 = <&pinctrl_i2c3>;
 244                         clocks = <&peri_clk 7>;
 245                         clock-frequency = <100000>;
 246                 };
 247
 248                 /* chip-internal connection for DMD */
 249                 i2c4: i2c@58784000 {
 250                         compatible = "socionext,uniphier-fi2c";
 251                         reg = <0x58784000 0x80>;
 252                         #address-cells = <1>;
 253                         #size-cells = <0>;
 254                         interrupts = <0 45 4>;
 255                         clocks = <&peri_clk 8>;
 256                         clock-frequency = <400000>;
 257                 };
 258
 259                 /* chip-internal connection for STM */
 260                 i2c5: i2c@58785000 {
 261                         compatible = "socionext,uniphier-fi2c";
 262                         reg = <0x58785000 0x80>;
 263                         #address-cells = <1>;
 264                         #size-cells = <0>;
 265                         interrupts = <0 25 4>;
 266                         clocks = <&peri_clk 9>;
 267                         clock-frequency = <400000>;
 268                 };
 269
 270                 /* chip-internal connection for HDMI */
 271                 i2c6: i2c@58786000 {
 272                         compatible = "socionext,uniphier-fi2c";
 273                         reg = <0x58786000 0x80>;
 274                         #address-cells = <1>;
 275                         #size-cells = <0>;
 276                         interrupts = <0 26 4>;
 277                         clocks = <&peri_clk 10>;
 278                         clock-frequency = <400000>;
 279                 };
 280
 281                 system_bus: system-bus@58c00000 {
 282                         compatible = "socionext,uniphier-system-bus";
 283                         status = "disabled";
 284                         reg = <0x58c00000 0x400>;
 285                         #address-cells = <2>;
 286                         #size-cells = <1>;
 287                         pinctrl-names = "default";
 288                         pinctrl-0 = <&pinctrl_system_bus>;
 289                 };
 290
 291                 smpctrl@59801000 {
 292                         compatible = "socionext,uniphier-smpctrl";
 293                         reg = <0x59801000 0x400>;
 294                 };
 295
 296                 sdctrl@59810000 {
 297                         compatible = "socionext,uniphier-pxs2-sdctrl",
 298                                      "simple-mfd", "syscon";
 299                         reg = <0x59810000 0x400>;
 300                         u-boot,dm-pre-reloc;
 301
 302                         sd_clk: clock {
 303                                 compatible = "socionext,uniphier-pxs2-sd-clock";
 304                                 #clock-cells = <1>;
 305                         };
 306
 307                         sd_rst: reset {
 308                                 compatible = "socionext,uniphier-pxs2-sd-reset";
 309                                 #reset-cells = <1>;
 310                         };
 311                 };
 312
 313                 perictrl@59820000 {
 314                         compatible = "socionext,uniphier-pxs2-perictrl",
 315                                      "simple-mfd", "syscon";
 316                         reg = <0x59820000 0x200>;
 317
 318                         peri_clk: clock {
 319                                 compatible = "socionext,uniphier-pxs2-peri-clock";
 320                                 #clock-cells = <1>;
 321                         };
 322
 323                         peri_rst: reset {
 324                                 compatible = "socionext,uniphier-pxs2-peri-reset";
 325                                 #reset-cells = <1>;
 326                         };
 327                 };
 328
 329                 emmc: sdhc@5a000000 {
 330                         compatible = "socionext,uniphier-sdhc";
 331                         status = "disabled";
 332                         reg = <0x5a000000 0x800>;
 333                         interrupts = <0 78 4>;
 334                         pinctrl-names = "default";
 335                         pinctrl-0 = <&pinctrl_emmc>;
 336                         clocks = <&sd_clk 1>;
 337                         reset-names = "host";
 338                         resets = <&sd_rst 1>;
 339                         bus-width = <8>;
 340                         non-removable;
 341                         cap-mmc-highspeed;
 342                         cap-mmc-hw-reset;
 343                         no-3-3-v;
 344                 };
 345
 346                 sd: sdhc@5a400000 {
 347                         compatible = "socionext,uniphier-sdhc";
 348                         status = "disabled";
 349                         reg = <0x5a400000 0x800>;
 350                         interrupts = <0 76 4>;
 351                         pinctrl-names = "default", "1.8v";
 352                         pinctrl-0 = <&pinctrl_sd>;
 353                         pinctrl-1 = <&pinctrl_sd_1v8>;
 354                         clocks = <&sd_clk 0>;
 355                         reset-names = "host";
 356                         resets = <&sd_rst 0>;
 357                         bus-width = <4>;
 358                         cap-sd-highspeed;
 359                         sd-uhs-sdr12;
 360                         sd-uhs-sdr25;
 361                         sd-uhs-sdr50;
 362                 };
 363
 364                 soc-glue@5f800000 {
 365                         compatible = "socionext,uniphier-pxs2-soc-glue",
 366                                      "simple-mfd", "syscon";
 367                         reg = <0x5f800000 0x2000>;
 368                         u-boot,dm-pre-reloc;
 369
 370                         pinctrl: pinctrl {
 371                                 compatible = "socionext,uniphier-pxs2-pinctrl";
 372                                 u-boot,dm-pre-reloc;
 373                         };
 374                 };
 375
 376                 aidet: aidet@5fc20000 {
 377                         compatible = "socionext,uniphier-pxs2-aidet";
 378                         reg = <0x5fc20000 0x200>;
 379                         interrupt-controller;
 380                         #interrupt-cells = <2>;
 381                 };
 382
 383                 timer@60000200 {
 384                         compatible = "arm,cortex-a9-global-timer";
 385                         reg = <0x60000200 0x20>;
 386                         interrupts = <1 11 0xf04>;
 387                         clocks = <&arm_timer_clk>;
 388                 };
 389
 390                 timer@60000600 {
 391                         compatible = "arm,cortex-a9-twd-timer";
 392                         reg = <0x60000600 0x20>;
 393                         interrupts = <1 13 0xf04>;
 394                         clocks = <&arm_timer_clk>;
 395                 };
 396
 397                 intc: interrupt-controller@60001000 {
 398                         compatible = "arm,cortex-a9-gic";
 399                         reg = <0x60001000 0x1000>,
 400                               <0x60000100 0x100>;
 401                         #interrupt-cells = <3>;
 402                         interrupt-controller;
 403                 };
 404
 405                 sysctrl@61840000 {
 406                         compatible = "socionext,uniphier-pxs2-sysctrl",
 407                                      "simple-mfd", "syscon";
 408                         reg = <0x61840000 0x10000>;
 409
 410                         sys_clk: clock {
 411                                 compatible = "socionext,uniphier-pxs2-clock";
 412                                 #clock-cells = <1>;
 413                         };
 414
 415                         sys_rst: reset {
 416                                 compatible = "socionext,uniphier-pxs2-reset";
 417                                 #reset-cells = <1>;
 418                         };
 419                 };
 420
 421                 usb0: usb@65b00000 {
 422                         compatible = "socionext,uniphier-pxs2-dwc3";
 423                         status = "disabled";
 424                         reg = <0x65b00000 0x1000>;
 425                         #address-cells = <1>;
 426                         #size-cells = <1>;
 427                         ranges;
 428                         pinctrl-names = "default";
 429                         pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
 430                         dwc3@65a00000 {
 431                                 compatible = "snps,dwc3";
 432                                 reg = <0x65a00000 0x10000>;
 433                                 interrupts = <0 134 4>;
 434                                 dr_mode = "host";
 435                                 tx-fifo-resize;
 436                         };
 437                 };
 438
 439                 usb1: usb@65d00000 {
 440                         compatible = "socionext,uniphier-pxs2-dwc3";
 441                         status = "disabled";
 442                         reg = <0x65d00000 0x1000>;
 443                         #address-cells = <1>;
 444                         #size-cells = <1>;
 445                         ranges;
 446                         pinctrl-names = "default";
 447                         pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
 448                         dwc3@65c00000 {
 449                                 compatible = "snps,dwc3";
 450                                 reg = <0x65c00000 0x10000>;
 451                                 interrupts = <0 137 4>;
 452                                 dr_mode = "host";
 453                                 tx-fifo-resize;
 454                         };
 455                 };
 456
 457                 nand: nand@68000000 {
 458                         compatible = "socionext,uniphier-denali-nand-v5b";
 459                         status = "disabled";
 460                         reg-names = "nand_data", "denali_reg";
 461                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 462                         interrupts = <0 65 4>;
 463                         pinctrl-names = "default";
 464                         pinctrl-0 = <&pinctrl_nand2cs>;
 465                         clocks = <&sys_clk 2>;
 466                 };
 467         };
 468 };
 469
 470 #include "uniphier-pinctrl.dtsi"