2 * Xilinx Zynq 7000 DTSI
3 * Describes the hardware common to all Zynq 7000-based boards.
5 * Copyright (C) 2011 - 2015 Xilinx
7 * SPDX-License-Identifier: GPL-2.0+
13 compatible = "xlnx,zynq-7000";
20 compatible = "arm,cortex-a9";
24 clock-latency = <1000>;
25 cpu0-supply = <®ulator_vccpint>;
34 compatible = "arm,cortex-a9";
42 compatible = "arm,cortex-a9-pmu";
43 interrupts = <0 5 4>, <0 6 4>;
44 interrupt-parent = <&intc>;
45 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
48 regulator_vccpint: fixedregulator {
49 compatible = "regulator-fixed";
50 regulator-name = "VCCPINT";
51 regulator-min-microvolt = <1000000>;
52 regulator-max-microvolt = <1000000>;
59 compatible = "simple-bus";
62 interrupt-parent = <&intc>;
66 compatible = "xlnx,zynq-xadc-1.00.a";
67 reg = <0xf8007100 0x20>;
69 interrupt-parent = <&intc>;
74 compatible = "xlnx,zynq-can-1.0";
76 clocks = <&clkc 19>, <&clkc 36>;
77 clock-names = "can_clk", "pclk";
78 reg = <0xe0008000 0x1000>;
79 interrupts = <0 28 4>;
80 interrupt-parent = <&intc>;
81 tx-fifo-depth = <0x40>;
82 rx-fifo-depth = <0x40>;
86 compatible = "xlnx,zynq-can-1.0";
88 clocks = <&clkc 20>, <&clkc 37>;
89 clock-names = "can_clk", "pclk";
90 reg = <0xe0009000 0x1000>;
91 interrupts = <0 51 4>;
92 interrupt-parent = <&intc>;
93 tx-fifo-depth = <0x40>;
94 rx-fifo-depth = <0x40>;
97 gpio0: gpio@e000a000 {
98 compatible = "xlnx,zynq-gpio-1.0";
100 #interrupt-cells = <2>;
103 interrupt-controller;
104 interrupt-parent = <&intc>;
105 interrupts = <0 20 4>;
106 reg = <0xe000a000 0x1000>;
110 compatible = "cdns,i2c-r1p10";
113 interrupt-parent = <&intc>;
114 interrupts = <0 25 4>;
115 reg = <0xe0004000 0x1000>;
116 #address-cells = <1>;
121 compatible = "cdns,i2c-r1p10";
124 interrupt-parent = <&intc>;
125 interrupts = <0 48 4>;
126 reg = <0xe0005000 0x1000>;
127 #address-cells = <1>;
131 intc: interrupt-controller@f8f01000 {
132 compatible = "arm,cortex-a9-gic";
133 #interrupt-cells = <3>;
134 interrupt-controller;
135 reg = <0xF8F01000 0x1000>,
139 L2: cache-controller@f8f02000 {
140 compatible = "arm,pl310-cache";
141 reg = <0xF8F02000 0x1000>;
142 interrupts = <0 2 4>;
143 arm,data-latency = <3 2 2>;
144 arm,tag-latency = <2 2 2>;
149 mc: memory-controller@f8006000 {
150 compatible = "xlnx,zynq-ddrc-a05";
151 reg = <0xf8006000 0x1000>;
154 uart0: serial@e0000000 {
155 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
157 clocks = <&clkc 23>, <&clkc 40>;
158 clock-names = "uart_clk", "pclk";
159 reg = <0xE0000000 0x1000>;
160 interrupts = <0 27 4>;
163 uart1: serial@e0001000 {
164 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
166 clocks = <&clkc 24>, <&clkc 41>;
167 clock-names = "uart_clk", "pclk";
168 reg = <0xE0001000 0x1000>;
169 interrupts = <0 50 4>;
173 compatible = "xlnx,zynq-spi-r1p6";
174 reg = <0xe0006000 0x1000>;
176 interrupt-parent = <&intc>;
177 interrupts = <0 26 4>;
178 clocks = <&clkc 25>, <&clkc 34>;
179 clock-names = "ref_clk", "pclk";
180 spi-max-frequency = <166666700>;
181 #address-cells = <1>;
186 compatible = "xlnx,zynq-spi-r1p6";
187 reg = <0xe0007000 0x1000>;
189 interrupt-parent = <&intc>;
190 interrupts = <0 49 4>;
191 clocks = <&clkc 26>, <&clkc 35>;
192 clock-names = "ref_clk", "pclk";
193 spi-max-frequency = <166666700>;
194 #address-cells = <1>;
199 clock-names = "ref_clk", "pclk";
200 clocks = <&clkc 10>, <&clkc 43>;
201 compatible = "xlnx,zynq-qspi-1.0";
203 interrupt-parent = <&intc>;
204 interrupts = <0 19 4>;
205 reg = <0xe000d000 0x1000>;
206 #address-cells = <1>;
210 gem0: ethernet@e000b000 {
211 compatible = "cdns,zynq-gem", "cdns,gem";
212 reg = <0xe000b000 0x1000>;
214 interrupts = <0 22 4>;
215 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
216 clock-names = "pclk", "hclk", "tx_clk";
217 #address-cells = <1>;
221 gem1: ethernet@e000c000 {
222 compatible = "cdns,zynq-gem", "cdns,gem";
223 reg = <0xe000c000 0x1000>;
225 interrupts = <0 45 4>;
226 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
227 clock-names = "pclk", "hclk", "tx_clk";
228 #address-cells = <1>;
232 sdhci0: sdhci@e0100000 {
233 compatible = "arasan,sdhci-8.9a";
235 clock-names = "clk_xin", "clk_ahb";
236 clocks = <&clkc 21>, <&clkc 32>;
237 interrupt-parent = <&intc>;
238 interrupts = <0 24 4>;
239 reg = <0xe0100000 0x1000>;
242 sdhci1: sdhci@e0101000 {
243 compatible = "arasan,sdhci-8.9a";
245 clock-names = "clk_xin", "clk_ahb";
246 clocks = <&clkc 22>, <&clkc 33>;
247 interrupt-parent = <&intc>;
248 interrupts = <0 47 4>;
249 reg = <0xe0101000 0x1000>;
252 slcr: slcr@f8000000 {
253 #address-cells = <1>;
255 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
256 reg = <0xF8000000 0x1000>;
260 compatible = "xlnx,ps7-clkc";
262 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
263 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
264 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
265 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
266 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
267 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
268 "gem1_aper", "sdio0_aper", "sdio1_aper",
269 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
270 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
271 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
272 "dbg_trc", "dbg_apb";
277 compatible = "xlnx,zynq-reset";
283 pinctrl0: pinctrl@700 {
284 compatible = "xlnx,pinctrl-zynq";
290 dmac_s: dmac@f8003000 {
291 compatible = "arm,pl330", "arm,primecell";
292 reg = <0xf8003000 0x1000>;
293 interrupt-parent = <&intc>;
294 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
295 "dma4", "dma5", "dma6", "dma7";
296 interrupts = <0 13 4>,
305 clock-names = "apb_pclk";
308 devcfg: devcfg@f8007000 {
309 compatible = "xlnx,zynq-devcfg-1.0";
310 interrupt-parent = <&intc>;
311 interrupts = <0 8 4>;
312 reg = <0xf8007000 0x100>;
313 clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
314 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
318 global_timer: timer@f8f00200 {
319 compatible = "arm,cortex-a9-global-timer";
320 reg = <0xf8f00200 0x20>;
321 interrupts = <1 11 0x301>;
322 interrupt-parent = <&intc>;
326 ttc0: timer@f8001000 {
327 interrupt-parent = <&intc>;
328 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
329 compatible = "cdns,ttc";
331 reg = <0xF8001000 0x1000>;
334 ttc1: timer@f8002000 {
335 interrupt-parent = <&intc>;
336 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
337 compatible = "cdns,ttc";
339 reg = <0xF8002000 0x1000>;
342 scutimer: timer@f8f00600 {
343 interrupt-parent = <&intc>;
344 interrupts = <1 13 0x301>;
345 compatible = "arm,cortex-a9-twd-timer";
346 reg = <0xf8f00600 0x20>;
351 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
354 interrupt-parent = <&intc>;
355 interrupts = <0 21 4>;
356 reg = <0xe0002000 0x1000>;
361 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
364 interrupt-parent = <&intc>;
365 interrupts = <0 44 4>;
366 reg = <0xe0003000 0x1000>;
370 watchdog0: watchdog@f8005000 {
372 compatible = "cdns,wdt-r1p2";
373 interrupt-parent = <&intc>;
374 interrupts = <0 9 1>;
375 reg = <0xf8005000 0x1000>;