1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU102 RevA
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 #include <dt-bindings/phy/phy.h>
19 model = "ZynqMP ZCU102 RevA";
20 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
42 device_type = "memory";
43 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
47 compatible = "gpio-keys";
53 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
54 linux,code = <108>; /* down */
61 compatible = "gpio-leds";
64 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "heartbeat";
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_can1_default>;
80 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
115 phy-handle = <&phy0>;
116 phy-mode = "rgmii-id";
117 pinctrl-names = "default";
118 pinctrl-0 = <&pinctrl_gem3_default>;
121 ti,rx-internal-delay = <0x8>;
122 ti,tx-internal-delay = <0xa>;
123 ti,fifo-depth = <0x1>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_gpio_default>;
139 clock-frequency = <400000>;
140 pinctrl-names = "default", "gpio";
141 pinctrl-0 = <&pinctrl_i2c0_default>;
142 pinctrl-1 = <&pinctrl_i2c0_gpio>;
143 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
144 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
146 tca6416_u97: gpio@20 {
148 * Enable all GTs to out from U-Boot
149 * i2c mw 20 6 0 - setup IO to output
150 * i2c mw 20 2 ef - setup output values on pins 0-7
151 * i2c mw 20 3 ff - setup output values on pins 10-17
153 compatible = "ti,tca6416";
160 * 0 - PS_GTR_LAN_SEL0
161 * 1 - PS_GTR_LAN_SEL1
162 * 2 - PS_GTR_LAN_SEL2
163 * 3 - PS_GTR_LAN_SEL3
164 * 4 - PCI_CLK_DIR_SEL
165 * 5 - IIC_MUX_RESET_B
166 * 6 - GEM3_EXP_RESET_B
167 * 7, 10 - 17 - not connected
173 output-low; /* PCIE = 0, DP = 1 */
179 output-high; /* PCIE = 0, DP = 1 */
185 output-high; /* PCIE = 0, USB0 = 1 */
191 output-high; /* PCIE = 0, SATA = 1 */
196 tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
197 compatible = "ti,tca6416";
208 * 4 - MIO26_PMU_INPUT_LS
211 * 7 - MAXIM_PMBUS_ALERT
212 * 10 - PL_DDR4_VTERM_EN
213 * 11 - PL_DDR4_VPP_2V5_EN
214 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
215 * 13 - PS_DIMM_SUSPEND_EN
216 * 14 - PS_DDR4_VTERM_EN
217 * 15 - PS_DDR4_VPP_2V5_EN
218 * 16 - 17 - not connected
222 i2c-mux@75 { /* u60 */
223 compatible = "nxp,pca9544";
224 #address-cells = <1>;
227 i2c@0 { /* i2c mw 75 0 1 */
228 #address-cells = <1>;
232 ina226@40 { /* u76 */
233 compatible = "ti,ina226";
235 shunt-resistor = <5000>;
237 ina226@41 { /* u77 */
238 compatible = "ti,ina226";
240 shunt-resistor = <5000>;
242 ina226@42 { /* u78 */
243 compatible = "ti,ina226";
245 shunt-resistor = <5000>;
247 ina226@43 { /* u87 */
248 compatible = "ti,ina226";
250 shunt-resistor = <5000>;
252 ina226@44 { /* u85 */
253 compatible = "ti,ina226";
255 shunt-resistor = <5000>;
257 ina226@45 { /* u86 */
258 compatible = "ti,ina226";
260 shunt-resistor = <5000>;
262 ina226@46 { /* u93 */
263 compatible = "ti,ina226";
265 shunt-resistor = <5000>;
267 ina226@47 { /* u88 */
268 compatible = "ti,ina226";
270 shunt-resistor = <5000>;
272 ina226@4a { /* u15 */
273 compatible = "ti,ina226";
275 shunt-resistor = <5000>;
277 ina226@4b { /* u92 */
278 compatible = "ti,ina226";
280 shunt-resistor = <5000>;
283 i2c@1 { /* i2c mw 75 0 1 */
284 #address-cells = <1>;
288 ina226@40 { /* u79 */
289 compatible = "ti,ina226";
291 shunt-resistor = <2000>;
293 ina226@41 { /* u81 */
294 compatible = "ti,ina226";
296 shunt-resistor = <5000>;
298 ina226@42 { /* u80 */
299 compatible = "ti,ina226";
301 shunt-resistor = <5000>;
303 ina226@43 { /* u84 */
304 compatible = "ti,ina226";
306 shunt-resistor = <5000>;
308 ina226@44 { /* u16 */
309 compatible = "ti,ina226";
311 shunt-resistor = <5000>;
313 ina226@45 { /* u65 */
314 compatible = "ti,ina226";
316 shunt-resistor = <5000>;
318 ina226@46 { /* u74 */
319 compatible = "ti,ina226";
321 shunt-resistor = <5000>;
323 ina226@47 { /* u75 */
324 compatible = "ti,ina226";
326 shunt-resistor = <5000>;
329 i2c@2 { /* i2c mw 75 0 1 */
330 #address-cells = <1>;
333 /* MAXIM_PMBUS - 00 */
334 max15301@a { /* u46 */
335 compatible = "maxim,max15301";
338 max15303@b { /* u4 */
339 compatible = "maxim,max15303";
342 max15303@10 { /* u13 */
343 compatible = "maxim,max15303";
346 max15301@13 { /* u47 */
347 compatible = "maxim,max15301";
350 max15303@14 { /* u7 */
351 compatible = "maxim,max15303";
354 max15303@15 { /* u6 */
355 compatible = "maxim,max15303";
358 max15303@16 { /* u10 */
359 compatible = "maxim,max15303";
362 max15303@17 { /* u9 */
363 compatible = "maxim,max15303";
366 max15301@18 { /* u63 */
367 compatible = "maxim,max15301";
370 max15303@1a { /* u49 */
371 compatible = "maxim,max15303";
374 max15303@1d { /* u18 */
375 compatible = "maxim,max15303";
378 max15303@20 { /* u8 */
379 compatible = "maxim,max15303";
380 status = "disabled"; /* unreachable */
384 /* drivers/hwmon/pmbus/Kconfig:86: be called max20751.
385 drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
387 max20751@72 { /* u95 FIXME - not detected */
388 compatible = "maxim,max20751";
391 max20751@73 { /* u96 FIXME - not detected */
392 compatible = "maxim,max20751";
396 /* Bus 3 is not connected */
399 /* FIXME PMOD - j160 */
400 /* FIXME MSP430F - u41 - not detected */
405 clock-frequency = <400000>;
406 pinctrl-names = "default", "gpio";
407 pinctrl-0 = <&pinctrl_i2c1_default>;
408 pinctrl-1 = <&pinctrl_i2c1_gpio>;
409 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
410 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
412 /* FIXME PL i2c via PCA9306 - u45 */
413 /* FIXME MSP430 - u41 - not detected */
414 i2c-mux@74 { /* u34 */
415 compatible = "nxp,pca9548";
416 #address-cells = <1>;
419 i2c@0 { /* i2c mw 74 0 1 */
420 #address-cells = <1>;
424 * IIC_EEPROM 1kB memory which uses 256B blocks
425 * where every block has different address.
426 * 0 - 256B address 0x54
427 * 256B - 512B address 0x55
428 * 512B - 768B address 0x56
429 * 768B - 1024B address 0x57
431 eeprom: eeprom@54 { /* u23 */
432 compatible = "at,24c08";
436 i2c@1 { /* i2c mw 74 0 2 */
437 #address-cells = <1>;
440 si5341: clock-generator1@36 { /* SI5341 - u69 */
441 compatible = "si5341";
446 i2c@2 { /* i2c mw 74 0 4 */
447 #address-cells = <1>;
450 si570_1: clock-generator2@5d { /* USER SI570 - u42 */
452 compatible = "silabs,si570";
454 temperature-stability = <50>;
455 factory-fout = <300000000>;
456 clock-frequency = <300000000>;
459 i2c@3 { /* i2c mw 74 0 8 */
460 #address-cells = <1>;
463 si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
465 compatible = "silabs,si570";
467 temperature-stability = <50>; /* copy from zc702 */
468 factory-fout = <156250000>;
469 clock-frequency = <148500000>;
472 i2c@4 { /* i2c mw 74 0 10 */
473 #address-cells = <1>;
476 si5328: clock-generator4@69 {/* SI5328 - u20 */
477 compatible = "silabs,si5328";
480 * Chip has interrupt present connected to PL
481 * interrupt-parent = <&>;
486 /* 5 - 7 unconnected */
490 compatible = "nxp,pca9548"; /* u135 */
491 #address-cells = <1>;
496 #address-cells = <1>;
502 #address-cells = <1>;
508 #address-cells = <1>;
513 i2c@3 { /* i2c mw 75 0 8 */
514 #address-cells = <1>;
518 dev@19 { /* u-boot detection */
522 dev@30 { /* u-boot detection */
526 dev@35 { /* u-boot detection */
530 dev@36 { /* u-boot detection */
534 dev@51 { /* u-boot detection - maybe SPD */
540 #address-cells = <1>;
546 #address-cells = <1>;
552 #address-cells = <1>;
558 #address-cells = <1>;
568 pinctrl_i2c0_default: i2c0-default {
570 groups = "i2c0_3_grp";
575 groups = "i2c0_3_grp";
577 slew-rate = <SLEW_RATE_SLOW>;
578 io-standard = <IO_STANDARD_LVCMOS18>;
582 pinctrl_i2c0_gpio: i2c0-gpio {
584 groups = "gpio0_14_grp", "gpio0_15_grp";
589 groups = "gpio0_14_grp", "gpio0_15_grp";
590 slew-rate = <SLEW_RATE_SLOW>;
591 io-standard = <IO_STANDARD_LVCMOS18>;
595 pinctrl_i2c1_default: i2c1-default {
597 groups = "i2c1_4_grp";
602 groups = "i2c1_4_grp";
604 slew-rate = <SLEW_RATE_SLOW>;
605 io-standard = <IO_STANDARD_LVCMOS18>;
609 pinctrl_i2c1_gpio: i2c1-gpio {
611 groups = "gpio0_16_grp", "gpio0_17_grp";
616 groups = "gpio0_16_grp", "gpio0_17_grp";
617 slew-rate = <SLEW_RATE_SLOW>;
618 io-standard = <IO_STANDARD_LVCMOS18>;
622 pinctrl_uart0_default: uart0-default {
624 groups = "uart0_4_grp";
629 groups = "uart0_4_grp";
630 slew-rate = <SLEW_RATE_SLOW>;
631 io-standard = <IO_STANDARD_LVCMOS18>;
645 pinctrl_uart1_default: uart1-default {
647 groups = "uart1_5_grp";
652 groups = "uart1_5_grp";
653 slew-rate = <SLEW_RATE_SLOW>;
654 io-standard = <IO_STANDARD_LVCMOS18>;
668 pinctrl_usb0_default: usb0-default {
670 groups = "usb0_0_grp";
675 groups = "usb0_0_grp";
676 slew-rate = <SLEW_RATE_SLOW>;
677 io-standard = <IO_STANDARD_LVCMOS18>;
681 pins = "MIO52", "MIO53", "MIO55";
686 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
687 "MIO60", "MIO61", "MIO62", "MIO63";
692 pinctrl_gem3_default: gem3-default {
694 function = "ethernet3";
695 groups = "ethernet3_0_grp";
699 groups = "ethernet3_0_grp";
700 slew-rate = <SLEW_RATE_SLOW>;
701 io-standard = <IO_STANDARD_LVCMOS18>;
705 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
712 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
720 groups = "mdio3_0_grp";
724 groups = "mdio3_0_grp";
725 slew-rate = <SLEW_RATE_SLOW>;
726 io-standard = <IO_STANDARD_LVCMOS18>;
731 pinctrl_can1_default: can1-default {
734 groups = "can1_6_grp";
738 groups = "can1_6_grp";
739 slew-rate = <SLEW_RATE_SLOW>;
740 io-standard = <IO_STANDARD_LVCMOS18>;
754 pinctrl_sdhci1_default: sdhci1-default {
756 groups = "sdio1_0_grp";
761 groups = "sdio1_0_grp";
762 slew-rate = <SLEW_RATE_SLOW>;
763 io-standard = <IO_STANDARD_LVCMOS18>;
768 groups = "sdio1_0_cd_grp";
769 function = "sdio1_cd";
773 groups = "sdio1_0_cd_grp";
776 slew-rate = <SLEW_RATE_SLOW>;
777 io-standard = <IO_STANDARD_LVCMOS18>;
781 groups = "sdio1_0_wp_grp";
782 function = "sdio1_wp";
786 groups = "sdio1_0_wp_grp";
789 slew-rate = <SLEW_RATE_SLOW>;
790 io-standard = <IO_STANDARD_LVCMOS18>;
794 pinctrl_gpio_default: gpio-default {
797 groups = "gpio0_22_grp", "gpio0_23_grp";
801 groups = "gpio0_22_grp", "gpio0_23_grp";
802 slew-rate = <SLEW_RATE_SLOW>;
803 io-standard = <IO_STANDARD_LVCMOS18>;
808 groups = "gpio0_13_grp", "gpio0_38_grp";
812 groups = "gpio0_13_grp", "gpio0_38_grp";
813 slew-rate = <SLEW_RATE_SLOW>;
814 io-standard = <IO_STANDARD_LVCMOS18>;
818 pins = "MIO22", "MIO23";
823 pins = "MIO13", "MIO38";
837 compatible = "m25p80"; /* 32MB */
838 #address-cells = <1>;
841 spi-tx-bus-width = <1>;
842 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
843 spi-max-frequency = <108000000>; /* Based on DC1 spec */
844 partition@qspi-fsbl-uboot { /* for testing purpose */
845 label = "qspi-fsbl-uboot";
846 reg = <0x0 0x100000>;
848 partition@qspi-linux { /* for testing purpose */
849 label = "qspi-linux";
850 reg = <0x100000 0x500000>;
852 partition@qspi-device-tree { /* for testing purpose */
853 label = "qspi-device-tree";
854 reg = <0x600000 0x20000>;
856 partition@qspi-rootfs { /* for testing purpose */
857 label = "qspi-rootfs";
858 reg = <0x620000 0x5E0000>;
869 /* SATA OOB timing settings */
870 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
871 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
872 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
873 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
874 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
875 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
876 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
877 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
878 phy-names = "sata-phy";
879 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
882 /* SD1 with level shifter */
885 pinctrl-names = "default";
886 pinctrl-0 = <&pinctrl_sdhci1_default>;
887 no-1-8-v; /* for 1.0 silicon */
897 pinctrl-names = "default";
898 pinctrl-0 = <&pinctrl_uart0_default>;
903 pinctrl-names = "default";
904 pinctrl-0 = <&pinctrl_uart1_default>;
907 /* ULPI SMSC USB3320 */
910 pinctrl-names = "default";
911 pinctrl-0 = <&pinctrl_usb0_default>;
917 snps,usb3_lpm_capable;
918 phy-names = "usb3-phy";
919 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
920 maximum-speed = "super-speed";
965 &xlnx_dp_snd_codec0 {