git.sur5r.net Git - u-boot/blob - arch/arm/dts/zynqmp-zcu102-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU102 RevA
   4  *
   5  * (C) Copyright 2015 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  16 #include <dt-bindings/phy/phy.h>
  17
  18 / {
  19         model = "ZynqMP ZCU102 RevA";
  20         compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem3;
  24                 gpio0 = &gpio;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 mmc0 = &sdhci1;
  28                 rtc0 = &rtc;
  29                 serial0 = &uart0;
  30                 serial1 = &uart1;
  31                 serial2 = &dcc;
  32                 spi0 = &qspi;
  33                 usb0 = &usb0;
  34         };
  35
  36         chosen {
  37                 bootargs = "earlycon";
  38                 stdout-path = "serial0:115200n8";
  39         };
  40
  41         memory@0 {
  42                 device_type = "memory";
  43                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  44         };
  45
  46         gpio-keys {
  47                 compatible = "gpio-keys";
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50                 autorepeat;
  51                 sw19 {
  52                         label = "sw19";
  53                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  54                         linux,code = <108>; /* down */
  55                         gpio-key,wakeup;
  56                         autorepeat;
  57                 };
  58         };
  59
  60         leds {
  61                 compatible = "gpio-leds";
  62                 heartbeat_led {
  63                         label = "heartbeat";
  64                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  65                         linux,default-trigger = "heartbeat";
  66                 };
  67         };
  68 };
  69
  70 &can1 {
  71         status = "okay";
  72         pinctrl-names = "default";
  73         pinctrl-0 = <&pinctrl_can1_default>;
  74 };
  75
  76 &dcc {
  77         status = "okay";
  78 };
  79
  80 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
  81 &fpd_dma_chan1 {
  82         status = "okay";
  83 };
  84
  85 &fpd_dma_chan2 {
  86         status = "okay";
  87 };
  88
  89 &fpd_dma_chan3 {
  90         status = "okay";
  91 };
  92
  93 &fpd_dma_chan4 {
  94         status = "okay";
  95 };
  96
  97 &fpd_dma_chan5 {
  98         status = "okay";
  99 };
 100
 101 &fpd_dma_chan6 {
 102         status = "okay";
 103 };
 104
 105 &fpd_dma_chan7 {
 106         status = "okay";
 107 };
 108
 109 &fpd_dma_chan8 {
 110         status = "okay";
 111 };
 112
 113 &gem3 {
 114         status = "okay";
 115         phy-handle = <&phy0>;
 116         phy-mode = "rgmii-id";
 117         pinctrl-names = "default";
 118         pinctrl-0 = <&pinctrl_gem3_default>;
 119         phy0: phy@21 {
 120                 reg = <21>;
 121                 ti,rx-internal-delay = <0x8>;
 122                 ti,tx-internal-delay = <0xa>;
 123                 ti,fifo-depth = <0x1>;
 124         };
 125 };
 126
 127 &gpio {
 128         status = "okay";
 129         pinctrl-names = "default";
 130         pinctrl-0 = <&pinctrl_gpio_default>;
 131 };
 132
 133 &gpu {
 134         status = "okay";
 135 };
 136
 137 &i2c0 {
 138         status = "okay";
 139         clock-frequency = <400000>;
 140         pinctrl-names = "default", "gpio";
 141         pinctrl-0 = <&pinctrl_i2c0_default>;
 142         pinctrl-1 = <&pinctrl_i2c0_gpio>;
 143         scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 144         sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 145
 146         tca6416_u97: gpio@20 {
 147                 /*
 148                  * Enable all GTs to out from U-Boot
 149                  * i2c mw 20 6 0  - setup IO to output
 150                  * i2c mw 20 2 ef - setup output values on pins 0-7
 151                  * i2c mw 20 3 ff - setup output values on pins 10-17
 152                  */
 153                 compatible = "ti,tca6416";
 154                 reg = <0x20>;
 155                 gpio-controller;
 156                 #gpio-cells = <2>;
 157                 /*
 158                  * IRQ not connected
 159                  * Lines:
 160                  * 0 - PS_GTR_LAN_SEL0
 161                  * 1 - PS_GTR_LAN_SEL1
 162                  * 2 - PS_GTR_LAN_SEL2
 163                  * 3 - PS_GTR_LAN_SEL3
 164                  * 4 - PCI_CLK_DIR_SEL
 165                  * 5 - IIC_MUX_RESET_B
 166                  * 6 - GEM3_EXP_RESET_B
 167                  * 7, 10 - 17 - not connected
 168                  */
 169
 170                 gtr_sel0 {
 171                         gpio-hog;
 172                         gpios = <0 0>;
 173                         output-low; /* PCIE = 0, DP = 1 */
 174                         line-name = "sel0";
 175                 };
 176                 gtr_sel1 {
 177                         gpio-hog;
 178                         gpios = <1 0>;
 179                         output-high; /* PCIE = 0, DP = 1 */
 180                         line-name = "sel1";
 181                 };
 182                 gtr_sel2 {
 183                         gpio-hog;
 184                         gpios = <2 0>;
 185                         output-high; /* PCIE = 0, USB0 = 1 */
 186                         line-name = "sel2";
 187                 };
 188                 gtr_sel3 {
 189                         gpio-hog;
 190                         gpios = <3 0>;
 191                         output-high; /* PCIE = 0, SATA = 1 */
 192                         line-name = "sel3";
 193                 };
 194         };
 195
 196         tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
 197                 compatible = "ti,tca6416";
 198                 reg = <0x21>;
 199                 gpio-controller;
 200                 #gpio-cells = <2>;
 201                 /*
 202                  * IRQ not connected
 203                  * Lines:
 204                  * 0 - VCCPSPLL_EN
 205                  * 1 - MGTRAVCC_EN
 206                  * 2 - MGTRAVTT_EN
 207                  * 3 - VCCPSDDRPLL_EN
 208                  * 4 - MIO26_PMU_INPUT_LS
 209                  * 5 - PL_PMBUS_ALERT
 210                  * 6 - PS_PMBUS_ALERT
 211                  * 7 - MAXIM_PMBUS_ALERT
 212                  * 10 - PL_DDR4_VTERM_EN
 213                  * 11 - PL_DDR4_VPP_2V5_EN
 214                  * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
 215                  * 13 - PS_DIMM_SUSPEND_EN
 216                  * 14 - PS_DDR4_VTERM_EN
 217                  * 15 - PS_DDR4_VPP_2V5_EN
 218                  * 16 - 17 - not connected
 219                  */
 220         };
 221
 222         i2c-mux@75 { /* u60 */
 223                 compatible = "nxp,pca9544";
 224                 #address-cells = <1>;
 225                 #size-cells = <0>;
 226                 reg = <0x75>;
 227                 i2c@0 { /* i2c mw 75 0 1 */
 228                         #address-cells = <1>;
 229                         #size-cells = <0>;
 230                         reg = <0>;
 231                         /* PS_PMBUS */
 232                         ina226@40 { /* u76 */
 233                                 compatible = "ti,ina226";
 234                                 reg = <0x40>;
 235                                 shunt-resistor = <5000>;
 236                         };
 237                         ina226@41 { /* u77 */
 238                                 compatible = "ti,ina226";
 239                                 reg = <0x41>;
 240                                 shunt-resistor = <5000>;
 241                         };
 242                         ina226@42 { /* u78 */
 243                                 compatible = "ti,ina226";
 244                                 reg = <0x42>;
 245                                 shunt-resistor = <5000>;
 246                         };
 247                         ina226@43 { /* u87 */
 248                                 compatible = "ti,ina226";
 249                                 reg = <0x43>;
 250                                 shunt-resistor = <5000>;
 251                         };
 252                         ina226@44 { /* u85 */
 253                                 compatible = "ti,ina226";
 254                                 reg = <0x44>;
 255                                 shunt-resistor = <5000>;
 256                         };
 257                         ina226@45 { /* u86 */
 258                                 compatible = "ti,ina226";
 259                                 reg = <0x45>;
 260                                 shunt-resistor = <5000>;
 261                         };
 262                         ina226@46 { /* u93 */
 263                                 compatible = "ti,ina226";
 264                                 reg = <0x46>;
 265                                 shunt-resistor = <5000>;
 266                         };
 267                         ina226@47 { /* u88 */
 268                                 compatible = "ti,ina226";
 269                                 reg = <0x47>;
 270                                 shunt-resistor = <5000>;
 271                         };
 272                         ina226@4a { /* u15 */
 273                                 compatible = "ti,ina226";
 274                                 reg = <0x4a>;
 275                                 shunt-resistor = <5000>;
 276                         };
 277                         ina226@4b { /* u92 */
 278                                 compatible = "ti,ina226";
 279                                 reg = <0x4b>;
 280                                 shunt-resistor = <5000>;
 281                         };
 282                 };
 283                 i2c@1 { /* i2c mw 75 0 1 */
 284                         #address-cells = <1>;
 285                         #size-cells = <0>;
 286                         reg = <1>;
 287                         /* PL_PMBUS */
 288                         ina226@40 { /* u79 */
 289                                 compatible = "ti,ina226";
 290                                 reg = <0x40>;
 291                                 shunt-resistor = <2000>;
 292                         };
 293                         ina226@41 { /* u81 */
 294                                 compatible = "ti,ina226";
 295                                 reg = <0x41>;
 296                                 shunt-resistor = <5000>;
 297                         };
 298                         ina226@42 { /* u80 */
 299                                 compatible = "ti,ina226";
 300                                 reg = <0x42>;
 301                                 shunt-resistor = <5000>;
 302                         };
 303                         ina226@43 { /* u84 */
 304                                 compatible = "ti,ina226";
 305                                 reg = <0x43>;
 306                                 shunt-resistor = <5000>;
 307                         };
 308                         ina226@44 { /* u16 */
 309                                 compatible = "ti,ina226";
 310                                 reg = <0x44>;
 311                                 shunt-resistor = <5000>;
 312                         };
 313                         ina226@45 { /* u65 */
 314                                 compatible = "ti,ina226";
 315                                 reg = <0x45>;
 316                                 shunt-resistor = <5000>;
 317                         };
 318                         ina226@46 { /* u74 */
 319                                 compatible = "ti,ina226";
 320                                 reg = <0x46>;
 321                                 shunt-resistor = <5000>;
 322                         };
 323                         ina226@47 { /* u75 */
 324                                 compatible = "ti,ina226";
 325                                 reg = <0x47>;
 326                                 shunt-resistor = <5000>;
 327                         };
 328                 };
 329                 i2c@2 { /* i2c mw 75 0 1 */
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                         reg = <2>;
 333                         /* MAXIM_PMBUS - 00 */
 334                         max15301@a { /* u46 */
 335                                 compatible = "maxim,max15301";
 336                                 reg = <0xa>;
 337                         };
 338                         max15303@b { /* u4 */
 339                                 compatible = "maxim,max15303";
 340                                 reg = <0xb>;
 341                         };
 342                         max15303@10 { /* u13 */
 343                                 compatible = "maxim,max15303";
 344                                 reg = <0x10>;
 345                         };
 346                         max15301@13 { /* u47 */
 347                                 compatible = "maxim,max15301";
 348                                 reg = <0x13>;
 349                         };
 350                         max15303@14 { /* u7 */
 351                                 compatible = "maxim,max15303";
 352                                 reg = <0x14>;
 353                         };
 354                         max15303@15 { /* u6 */
 355                                 compatible = "maxim,max15303";
 356                                 reg = <0x15>;
 357                         };
 358                         max15303@16 { /* u10 */
 359                                 compatible = "maxim,max15303";
 360                                 reg = <0x16>;
 361                         };
 362                         max15303@17 { /* u9 */
 363                                 compatible = "maxim,max15303";
 364                                 reg = <0x17>;
 365                         };
 366                         max15301@18 { /* u63 */
 367                                 compatible = "maxim,max15301";
 368                                 reg = <0x18>;
 369                         };
 370                         max15303@1a { /* u49 */
 371                                 compatible = "maxim,max15303";
 372                                 reg = <0x1a>;
 373                         };
 374                         max15303@1d { /* u18 */
 375                                 compatible = "maxim,max15303";
 376                                 reg = <0x1d>;
 377                         };
 378                         max15303@20 { /* u8 */
 379                                 compatible = "maxim,max15303";
 380                                 status = "disabled"; /* unreachable */
 381                                 reg = <0x20>;
 382                         };
 383
 384 /*                      drivers/hwmon/pmbus/Kconfig:86:   be called max20751.
 385 drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 386 */
 387                         max20751@72 { /* u95 FIXME - not detected */
 388                                 compatible = "maxim,max20751";
 389                                 reg = <0x72>;
 390                         };
 391                         max20751@73 { /* u96 FIXME - not detected */
 392                                 compatible = "maxim,max20751";
 393                                 reg = <0x73>;
 394                         };
 395                 };
 396                 /* Bus 3 is not connected */
 397         };
 398
 399         /* FIXME PMOD - j160 */
 400         /* FIXME MSP430F - u41 - not detected */
 401 };
 402
 403 &i2c1 {
 404         status = "okay";
 405         clock-frequency = <400000>;
 406         pinctrl-names = "default", "gpio";
 407         pinctrl-0 = <&pinctrl_i2c1_default>;
 408         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 409         scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 410         sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 411
 412         /* FIXME PL i2c via PCA9306 - u45 */
 413         /* FIXME MSP430 - u41 - not detected */
 414         i2c-mux@74 { /* u34 */
 415                 compatible = "nxp,pca9548";
 416                 #address-cells = <1>;
 417                 #size-cells = <0>;
 418                 reg = <0x74>;
 419                 i2c@0 { /* i2c mw 74 0 1 */
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422                         reg = <0>;
 423                         /*
 424                          * IIC_EEPROM 1kB memory which uses 256B blocks
 425                          * where every block has different address.
 426                          *    0 - 256B address 0x54
 427                          * 256B - 512B address 0x55
 428                          * 512B - 768B address 0x56
 429                          * 768B - 1024B address 0x57
 430                          */
 431                         eeprom: eeprom@54 { /* u23 */
 432                                 compatible = "at,24c08";
 433                                 reg = <0x54>;
 434                         };
 435                 };
 436                 i2c@1 { /* i2c mw 74 0 2 */
 437                         #address-cells = <1>;
 438                         #size-cells = <0>;
 439                         reg = <1>;
 440                         si5341: clock-generator1@36 { /* SI5341 - u69 */
 441                                 compatible = "si5341";
 442                                 reg = <0x36>;
 443                         };
 444
 445                 };
 446                 i2c@2 { /* i2c mw 74 0 4 */
 447                         #address-cells = <1>;
 448                         #size-cells = <0>;
 449                         reg = <2>;
 450                         si570_1: clock-generator2@5d { /* USER SI570 - u42 */
 451                                 #clock-cells = <0>;
 452                                 compatible = "silabs,si570";
 453                                 reg = <0x5d>;
 454                                 temperature-stability = <50>;
 455                                 factory-fout = <300000000>;
 456                                 clock-frequency = <300000000>;
 457                         };
 458                 };
 459                 i2c@3 { /* i2c mw 74 0 8 */
 460                         #address-cells = <1>;
 461                         #size-cells = <0>;
 462                         reg = <3>;
 463                         si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
 464                                 #clock-cells = <0>;
 465                                 compatible = "silabs,si570";
 466                                 reg = <0x5d>;
 467                                 temperature-stability = <50>; /* copy from zc702 */
 468                                 factory-fout = <156250000>;
 469                                 clock-frequency = <148500000>;
 470                         };
 471                 };
 472                 i2c@4 { /* i2c mw 74 0 10 */
 473                         #address-cells = <1>;
 474                         #size-cells = <0>;
 475                         reg = <4>;
 476                         si5328: clock-generator4@69 {/* SI5328 - u20 */
 477                                 compatible = "silabs,si5328";
 478                                 reg = <0x69>;
 479                                 /*
 480                                  * Chip has interrupt present connected to PL
 481                                  * interrupt-parent = <&>;
 482                                  * interrupts = <>;
 483                                  */
 484                         };
 485                 };
 486                 /* 5 - 7 unconnected */
 487         };
 488
 489         i2c-mux@75 {
 490                 compatible = "nxp,pca9548"; /* u135 */
 491                 #address-cells = <1>;
 492                 #size-cells = <0>;
 493                 reg = <0x75>;
 494
 495                 i2c@0 {
 496                         #address-cells = <1>;
 497                         #size-cells = <0>;
 498                         reg = <0>;
 499                         /* HPC0_IIC */
 500                 };
 501                 i2c@1 {
 502                         #address-cells = <1>;
 503                         #size-cells = <0>;
 504                         reg = <1>;
 505                         /* HPC1_IIC */
 506                 };
 507                 i2c@2 {
 508                         #address-cells = <1>;
 509                         #size-cells = <0>;
 510                         reg = <2>;
 511                         /* SYSMON */
 512                 };
 513                 i2c@3 { /* i2c mw 75 0 8 */
 514                         #address-cells = <1>;
 515                         #size-cells = <0>;
 516                         reg = <3>;
 517                         /* DDR4 SODIMM */
 518                         dev@19 { /* u-boot detection */
 519                                 compatible = "xxx";
 520                                 reg = <0x19>;
 521                         };
 522                         dev@30 { /* u-boot detection */
 523                                 compatible = "xxx";
 524                                 reg = <0x30>;
 525                         };
 526                         dev@35 { /* u-boot detection */
 527                                 compatible = "xxx";
 528                                 reg = <0x35>;
 529                         };
 530                         dev@36 { /* u-boot detection */
 531                                 compatible = "xxx";
 532                                 reg = <0x36>;
 533                         };
 534                         dev@51 { /* u-boot detection - maybe SPD */
 535                                 compatible = "xxx";
 536                                 reg = <0x51>;
 537                         };
 538                 };
 539                 i2c@4 {
 540                         #address-cells = <1>;
 541                         #size-cells = <0>;
 542                         reg = <4>;
 543                         /* SEP 3 */
 544                 };
 545                 i2c@5 {
 546                         #address-cells = <1>;
 547                         #size-cells = <0>;
 548                         reg = <5>;
 549                         /* SEP 2 */
 550                 };
 551                 i2c@6 {
 552                         #address-cells = <1>;
 553                         #size-cells = <0>;
 554                         reg = <6>;
 555                         /* SEP 1 */
 556                 };
 557                 i2c@7 {
 558                         #address-cells = <1>;
 559                         #size-cells = <0>;
 560                         reg = <7>;
 561                         /* SEP 0 */
 562                 };
 563         };
 564 };
 565
 566 &pinctrl0 {
 567         status = "okay";
 568         pinctrl_i2c0_default: i2c0-default {
 569                 mux {
 570                         groups = "i2c0_3_grp";
 571                         function = "i2c0";
 572                 };
 573
 574                 conf {
 575                         groups = "i2c0_3_grp";
 576                         bias-pull-up;
 577                         slew-rate = <SLEW_RATE_SLOW>;
 578                         io-standard = <IO_STANDARD_LVCMOS18>;
 579                 };
 580         };
 581
 582         pinctrl_i2c0_gpio: i2c0-gpio {
 583                 mux {
 584                         groups = "gpio0_14_grp", "gpio0_15_grp";
 585                         function = "gpio0";
 586                 };
 587
 588                 conf {
 589                         groups = "gpio0_14_grp", "gpio0_15_grp";
 590                         slew-rate = <SLEW_RATE_SLOW>;
 591                         io-standard = <IO_STANDARD_LVCMOS18>;
 592                 };
 593         };
 594
 595         pinctrl_i2c1_default: i2c1-default {
 596                 mux {
 597                         groups = "i2c1_4_grp";
 598                         function = "i2c1";
 599                 };
 600
 601                 conf {
 602                         groups = "i2c1_4_grp";
 603                         bias-pull-up;
 604                         slew-rate = <SLEW_RATE_SLOW>;
 605                         io-standard = <IO_STANDARD_LVCMOS18>;
 606                 };
 607         };
 608
 609         pinctrl_i2c1_gpio: i2c1-gpio {
 610                 mux {
 611                         groups = "gpio0_16_grp", "gpio0_17_grp";
 612                         function = "gpio0";
 613                 };
 614
 615                 conf {
 616                         groups = "gpio0_16_grp", "gpio0_17_grp";
 617                         slew-rate = <SLEW_RATE_SLOW>;
 618                         io-standard = <IO_STANDARD_LVCMOS18>;
 619                 };
 620         };
 621
 622         pinctrl_uart0_default: uart0-default {
 623                 mux {
 624                         groups = "uart0_4_grp";
 625                         function = "uart0";
 626                 };
 627
 628                 conf {
 629                         groups = "uart0_4_grp";
 630                         slew-rate = <SLEW_RATE_SLOW>;
 631                         io-standard = <IO_STANDARD_LVCMOS18>;
 632                 };
 633
 634                 conf-rx {
 635                         pins = "MIO18";
 636                         bias-high-impedance;
 637                 };
 638
 639                 conf-tx {
 640                         pins = "MIO19";
 641                         bias-disable;
 642                 };
 643         };
 644
 645         pinctrl_uart1_default: uart1-default {
 646                 mux {
 647                         groups = "uart1_5_grp";
 648                         function = "uart1";
 649                 };
 650
 651                 conf {
 652                         groups = "uart1_5_grp";
 653                         slew-rate = <SLEW_RATE_SLOW>;
 654                         io-standard = <IO_STANDARD_LVCMOS18>;
 655                 };
 656
 657                 conf-rx {
 658                         pins = "MIO21";
 659                         bias-high-impedance;
 660                 };
 661
 662                 conf-tx {
 663                         pins = "MIO20";
 664                         bias-disable;
 665                 };
 666         };
 667
 668         pinctrl_usb0_default: usb0-default {
 669                 mux {
 670                         groups = "usb0_0_grp";
 671                         function = "usb0";
 672                 };
 673
 674                 conf {
 675                         groups = "usb0_0_grp";
 676                         slew-rate = <SLEW_RATE_SLOW>;
 677                         io-standard = <IO_STANDARD_LVCMOS18>;
 678                 };
 679
 680                 conf-rx {
 681                         pins = "MIO52", "MIO53", "MIO55";
 682                         bias-high-impedance;
 683                 };
 684
 685                 conf-tx {
 686                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 687                                "MIO60", "MIO61", "MIO62", "MIO63";
 688                         bias-disable;
 689                 };
 690         };
 691
 692         pinctrl_gem3_default: gem3-default {
 693                 mux {
 694                         function = "ethernet3";
 695                         groups = "ethernet3_0_grp";
 696                 };
 697
 698                 conf {
 699                         groups = "ethernet3_0_grp";
 700                         slew-rate = <SLEW_RATE_SLOW>;
 701                         io-standard = <IO_STANDARD_LVCMOS18>;
 702                 };
 703
 704                 conf-rx {
 705                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 706                                                                         "MIO75";
 707                         bias-high-impedance;
 708                         low-power-disable;
 709                 };
 710
 711                 conf-tx {
 712                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 713                                                                         "MIO69";
 714                         bias-disable;
 715                         low-power-enable;
 716                 };
 717
 718                 mux-mdio {
 719                         function = "mdio3";
 720                         groups = "mdio3_0_grp";
 721                 };
 722
 723                 conf-mdio {
 724                         groups = "mdio3_0_grp";
 725                         slew-rate = <SLEW_RATE_SLOW>;
 726                         io-standard = <IO_STANDARD_LVCMOS18>;
 727                         bias-disable;
 728                 };
 729         };
 730
 731         pinctrl_can1_default: can1-default {
 732                 mux {
 733                         function = "can1";
 734                         groups = "can1_6_grp";
 735                 };
 736
 737                 conf {
 738                         groups = "can1_6_grp";
 739                         slew-rate = <SLEW_RATE_SLOW>;
 740                         io-standard = <IO_STANDARD_LVCMOS18>;
 741                 };
 742
 743                 conf-rx {
 744                         pins = "MIO25";
 745                         bias-high-impedance;
 746                 };
 747
 748                 conf-tx {
 749                         pins = "MIO24";
 750                         bias-disable;
 751                 };
 752         };
 753
 754         pinctrl_sdhci1_default: sdhci1-default {
 755                 mux {
 756                         groups = "sdio1_0_grp";
 757                         function = "sdio1";
 758                 };
 759
 760                 conf {
 761                         groups = "sdio1_0_grp";
 762                         slew-rate = <SLEW_RATE_SLOW>;
 763                         io-standard = <IO_STANDARD_LVCMOS18>;
 764                         bias-disable;
 765                 };
 766
 767                 mux-cd {
 768                         groups = "sdio1_0_cd_grp";
 769                         function = "sdio1_cd";
 770                 };
 771
 772                 conf-cd {
 773                         groups = "sdio1_0_cd_grp";
 774                         bias-high-impedance;
 775                         bias-pull-up;
 776                         slew-rate = <SLEW_RATE_SLOW>;
 777                         io-standard = <IO_STANDARD_LVCMOS18>;
 778                 };
 779
 780                 mux-wp {
 781                         groups = "sdio1_0_wp_grp";
 782                         function = "sdio1_wp";
 783                 };
 784
 785                 conf-wp {
 786                         groups = "sdio1_0_wp_grp";
 787                         bias-high-impedance;
 788                         bias-pull-up;
 789                         slew-rate = <SLEW_RATE_SLOW>;
 790                         io-standard = <IO_STANDARD_LVCMOS18>;
 791                 };
 792         };
 793
 794         pinctrl_gpio_default: gpio-default {
 795                 mux-sw {
 796                         function = "gpio0";
 797                         groups = "gpio0_22_grp", "gpio0_23_grp";
 798                 };
 799
 800                 conf-sw {
 801                         groups = "gpio0_22_grp", "gpio0_23_grp";
 802                         slew-rate = <SLEW_RATE_SLOW>;
 803                         io-standard = <IO_STANDARD_LVCMOS18>;
 804                 };
 805
 806                 mux-msp {
 807                         function = "gpio0";
 808                         groups = "gpio0_13_grp", "gpio0_38_grp";
 809                 };
 810
 811                 conf-msp {
 812                         groups = "gpio0_13_grp", "gpio0_38_grp";
 813                         slew-rate = <SLEW_RATE_SLOW>;
 814                         io-standard = <IO_STANDARD_LVCMOS18>;
 815                 };
 816
 817                 conf-pull-up {
 818                         pins = "MIO22", "MIO23";
 819                         bias-pull-up;
 820                 };
 821
 822                 conf-pull-none {
 823                         pins = "MIO13", "MIO38";
 824                         bias-disable;
 825                 };
 826         };
 827 };
 828
 829 &pcie {
 830         status = "okay";
 831 };
 832
 833 &qspi {
 834         status = "okay";
 835         is-dual = <1>;
 836         flash@0 {
 837                 compatible = "m25p80"; /* 32MB */
 838                 #address-cells = <1>;
 839                 #size-cells = <1>;
 840                 reg = <0x0>;
 841                 spi-tx-bus-width = <1>;
 842                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 843                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 844                 partition@qspi-fsbl-uboot { /* for testing purpose */
 845                         label = "qspi-fsbl-uboot";
 846                         reg = <0x0 0x100000>;
 847                 };
 848                 partition@qspi-linux { /* for testing purpose */
 849                         label = "qspi-linux";
 850                         reg = <0x100000 0x500000>;
 851                 };
 852                 partition@qspi-device-tree { /* for testing purpose */
 853                         label = "qspi-device-tree";
 854                         reg = <0x600000 0x20000>;
 855                 };
 856                 partition@qspi-rootfs { /* for testing purpose */
 857                         label = "qspi-rootfs";
 858                         reg = <0x620000 0x5E0000>;
 859                 };
 860         };
 861 };
 862
 863 &rtc {
 864         status = "okay";
 865 };
 866
 867 &sata {
 868         status = "okay";
 869         /* SATA OOB timing settings */
 870         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 871         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 872         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 873         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 874         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 875         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 876         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 877         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 878         phy-names = "sata-phy";
 879         phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
 880 };
 881
 882 /* SD1 with level shifter */
 883 &sdhci1 {
 884         status = "okay";
 885         pinctrl-names = "default";
 886         pinctrl-0 = <&pinctrl_sdhci1_default>;
 887         no-1-8-v;       /* for 1.0 silicon */
 888         xlnx,mio_bank = <1>;
 889 };
 890
 891 &serdes {
 892         status = "okay";
 893 };
 894
 895 &uart0 {
 896         status = "okay";
 897         pinctrl-names = "default";
 898         pinctrl-0 = <&pinctrl_uart0_default>;
 899 };
 900
 901 &uart1 {
 902         status = "okay";
 903         pinctrl-names = "default";
 904         pinctrl-0 = <&pinctrl_uart1_default>;
 905 };
 906
 907 /* ULPI SMSC USB3320 */
 908 &usb0 {
 909         status = "okay";
 910         pinctrl-names = "default";
 911         pinctrl-0 = <&pinctrl_usb0_default>;
 912 };
 913
 914 &dwc3_0 {
 915         status = "okay";
 916         dr_mode = "host";
 917         snps,usb3_lpm_capable;
 918         phy-names = "usb3-phy";
 919         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 920         maximum-speed = "super-speed";
 921 };
 922
 923 &watchdog0 {
 924         status = "okay";
 925 };
 926
 927 &xilinx_ams {
 928         status = "okay";
 929 };
 930
 931 &ams_ps {
 932         status = "okay";
 933 };
 934
 935 &ams_pl {
 936         status = "okay";
 937 };
 938
 939 &xilinx_drm {
 940         status = "okay";
 941         clocks = <&si570_1>;
 942 };
 943
 944 &xlnx_dp {
 945         status = "okay";
 946 };
 947
 948 &xlnx_dp_sub {
 949         status = "okay";
 950         xlnx,vid-clk-pl;
 951 };
 952
 953 &xlnx_dp_snd_pcm0 {
 954         status = "okay";
 955 };
 956
 957 &xlnx_dp_snd_pcm1 {
 958         status = "okay";
 959 };
 960
 961 &xlnx_dp_snd_card {
 962         status = "okay";
 963 };
 964
 965 &xlnx_dp_snd_codec0 {
 966         status = "okay";
 967 };
 968
 969 &xlnx_dpdma {
 970         status = "okay";
 971 };