1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU102 RevA
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 #include <dt-bindings/phy/phy.h>
19 model = "ZynqMP ZCU102 RevA";
20 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
42 device_type = "memory";
43 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
47 compatible = "gpio-keys";
53 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
54 linux,code = <108>; /* down */
61 compatible = "gpio-leds";
64 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "heartbeat";
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_can1_default>;
114 phy-handle = <&phy0>;
115 phy-mode = "rgmii-id";
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_gem3_default>;
120 ti,rx-internal-delay = <0x8>;
121 ti,tx-internal-delay = <0xa>;
122 ti,fifo-depth = <0x1>;
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_gpio_default>;
138 clock-frequency = <400000>;
139 pinctrl-names = "default", "gpio";
140 pinctrl-0 = <&pinctrl_i2c0_default>;
141 pinctrl-1 = <&pinctrl_i2c0_gpio>;
142 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
143 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
145 tca6416_u97: gpio@20 {
147 * Enable all GTs to out from U-Boot
148 * i2c mw 20 6 0 - setup IO to output
149 * i2c mw 20 2 ef - setup output values on pins 0-7
150 * i2c mw 20 3 ff - setup output values on pins 10-17
152 compatible = "ti,tca6416";
159 * 0 - PS_GTR_LAN_SEL0
160 * 1 - PS_GTR_LAN_SEL1
161 * 2 - PS_GTR_LAN_SEL2
162 * 3 - PS_GTR_LAN_SEL3
163 * 4 - PCI_CLK_DIR_SEL
164 * 5 - IIC_MUX_RESET_B
165 * 6 - GEM3_EXP_RESET_B
166 * 7, 10 - 17 - not connected
172 output-low; /* PCIE = 0, DP = 1 */
178 output-high; /* PCIE = 0, DP = 1 */
184 output-high; /* PCIE = 0, USB0 = 1 */
190 output-high; /* PCIE = 0, SATA = 1 */
195 tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
196 compatible = "ti,tca6416";
207 * 4 - MIO26_PMU_INPUT_LS
210 * 7 - MAXIM_PMBUS_ALERT
211 * 10 - PL_DDR4_VTERM_EN
212 * 11 - PL_DDR4_VPP_2V5_EN
213 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
214 * 13 - PS_DIMM_SUSPEND_EN
215 * 14 - PS_DDR4_VTERM_EN
216 * 15 - PS_DDR4_VPP_2V5_EN
217 * 16 - 17 - not connected
221 i2c-mux@75 { /* u60 */
222 compatible = "nxp,pca9544";
223 #address-cells = <1>;
226 i2c@0 { /* i2c mw 75 0 1 */
227 #address-cells = <1>;
231 ina226@40 { /* u76 */
232 compatible = "ti,ina226";
234 shunt-resistor = <5000>;
236 ina226@41 { /* u77 */
237 compatible = "ti,ina226";
239 shunt-resistor = <5000>;
241 ina226@42 { /* u78 */
242 compatible = "ti,ina226";
244 shunt-resistor = <5000>;
246 ina226@43 { /* u87 */
247 compatible = "ti,ina226";
249 shunt-resistor = <5000>;
251 ina226@44 { /* u85 */
252 compatible = "ti,ina226";
254 shunt-resistor = <5000>;
256 ina226@45 { /* u86 */
257 compatible = "ti,ina226";
259 shunt-resistor = <5000>;
261 ina226@46 { /* u93 */
262 compatible = "ti,ina226";
264 shunt-resistor = <5000>;
266 ina226@47 { /* u88 */
267 compatible = "ti,ina226";
269 shunt-resistor = <5000>;
271 ina226@4a { /* u15 */
272 compatible = "ti,ina226";
274 shunt-resistor = <5000>;
276 ina226@4b { /* u92 */
277 compatible = "ti,ina226";
279 shunt-resistor = <5000>;
282 i2c@1 { /* i2c mw 75 0 1 */
283 #address-cells = <1>;
287 ina226@40 { /* u79 */
288 compatible = "ti,ina226";
290 shunt-resistor = <2000>;
292 ina226@41 { /* u81 */
293 compatible = "ti,ina226";
295 shunt-resistor = <5000>;
297 ina226@42 { /* u80 */
298 compatible = "ti,ina226";
300 shunt-resistor = <5000>;
302 ina226@43 { /* u84 */
303 compatible = "ti,ina226";
305 shunt-resistor = <5000>;
307 ina226@44 { /* u16 */
308 compatible = "ti,ina226";
310 shunt-resistor = <5000>;
312 ina226@45 { /* u65 */
313 compatible = "ti,ina226";
315 shunt-resistor = <5000>;
317 ina226@46 { /* u74 */
318 compatible = "ti,ina226";
320 shunt-resistor = <5000>;
322 ina226@47 { /* u75 */
323 compatible = "ti,ina226";
325 shunt-resistor = <5000>;
328 i2c@2 { /* i2c mw 75 0 1 */
329 #address-cells = <1>;
332 /* MAXIM_PMBUS - 00 */
333 max15301@a { /* u46 */
334 compatible = "maxim,max15301";
337 max15303@b { /* u4 */
338 compatible = "maxim,max15303";
341 max15303@10 { /* u13 */
342 compatible = "maxim,max15303";
345 max15301@13 { /* u47 */
346 compatible = "maxim,max15301";
349 max15303@14 { /* u7 */
350 compatible = "maxim,max15303";
353 max15303@15 { /* u6 */
354 compatible = "maxim,max15303";
357 max15303@16 { /* u10 */
358 compatible = "maxim,max15303";
361 max15303@17 { /* u9 */
362 compatible = "maxim,max15303";
365 max15301@18 { /* u63 */
366 compatible = "maxim,max15301";
369 max15303@1a { /* u49 */
370 compatible = "maxim,max15303";
373 max15303@1d { /* u18 */
374 compatible = "maxim,max15303";
377 max15303@20 { /* u8 */
378 compatible = "maxim,max15303";
379 status = "disabled"; /* unreachable */
383 max20751@72 { /* u95 */
384 compatible = "maxim,max20751";
387 max20751@73 { /* u96 */
388 compatible = "maxim,max20751";
392 /* Bus 3 is not connected */
398 clock-frequency = <400000>;
399 pinctrl-names = "default", "gpio";
400 pinctrl-0 = <&pinctrl_i2c1_default>;
401 pinctrl-1 = <&pinctrl_i2c1_gpio>;
402 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
403 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
405 /* PL i2c via PCA9306 - u45 */
406 i2c-mux@74 { /* u34 */
407 compatible = "nxp,pca9548";
408 #address-cells = <1>;
411 i2c@0 { /* i2c mw 74 0 1 */
412 #address-cells = <1>;
416 * IIC_EEPROM 1kB memory which uses 256B blocks
417 * where every block has different address.
418 * 0 - 256B address 0x54
419 * 256B - 512B address 0x55
420 * 512B - 768B address 0x56
421 * 768B - 1024B address 0x57
423 eeprom: eeprom@54 { /* u23 */
424 compatible = "at,24c08";
428 i2c@1 { /* i2c mw 74 0 2 */
429 #address-cells = <1>;
432 si5341: clock-generator1@36 { /* SI5341 - u69 */
433 compatible = "si5341";
438 i2c@2 { /* i2c mw 74 0 4 */
439 #address-cells = <1>;
442 si570_1: clock-generator2@5d { /* USER SI570 - u42 */
444 compatible = "silabs,si570";
446 temperature-stability = <50>;
447 factory-fout = <300000000>;
448 clock-frequency = <300000000>;
451 i2c@3 { /* i2c mw 74 0 8 */
452 #address-cells = <1>;
455 si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
457 compatible = "silabs,si570";
459 temperature-stability = <50>; /* copy from zc702 */
460 factory-fout = <156250000>;
461 clock-frequency = <148500000>;
464 i2c@4 { /* i2c mw 74 0 10 */
465 #address-cells = <1>;
468 si5328: clock-generator4@69 {/* SI5328 - u20 */
469 compatible = "silabs,si5328";
472 * Chip has interrupt present connected to PL
473 * interrupt-parent = <&>;
478 /* 5 - 7 unconnected */
482 compatible = "nxp,pca9548"; /* u135 */
483 #address-cells = <1>;
488 #address-cells = <1>;
494 #address-cells = <1>;
500 #address-cells = <1>;
505 i2c@3 { /* i2c mw 75 0 8 */
506 #address-cells = <1>;
527 #address-cells = <1>;
533 #address-cells = <1>;
539 #address-cells = <1>;
545 #address-cells = <1>;
555 pinctrl_i2c0_default: i2c0-default {
557 groups = "i2c0_3_grp";
562 groups = "i2c0_3_grp";
564 slew-rate = <SLEW_RATE_SLOW>;
565 io-standard = <IO_STANDARD_LVCMOS18>;
569 pinctrl_i2c0_gpio: i2c0-gpio {
571 groups = "gpio0_14_grp", "gpio0_15_grp";
576 groups = "gpio0_14_grp", "gpio0_15_grp";
577 slew-rate = <SLEW_RATE_SLOW>;
578 io-standard = <IO_STANDARD_LVCMOS18>;
582 pinctrl_i2c1_default: i2c1-default {
584 groups = "i2c1_4_grp";
589 groups = "i2c1_4_grp";
591 slew-rate = <SLEW_RATE_SLOW>;
592 io-standard = <IO_STANDARD_LVCMOS18>;
596 pinctrl_i2c1_gpio: i2c1-gpio {
598 groups = "gpio0_16_grp", "gpio0_17_grp";
603 groups = "gpio0_16_grp", "gpio0_17_grp";
604 slew-rate = <SLEW_RATE_SLOW>;
605 io-standard = <IO_STANDARD_LVCMOS18>;
609 pinctrl_uart0_default: uart0-default {
611 groups = "uart0_4_grp";
616 groups = "uart0_4_grp";
617 slew-rate = <SLEW_RATE_SLOW>;
618 io-standard = <IO_STANDARD_LVCMOS18>;
632 pinctrl_uart1_default: uart1-default {
634 groups = "uart1_5_grp";
639 groups = "uart1_5_grp";
640 slew-rate = <SLEW_RATE_SLOW>;
641 io-standard = <IO_STANDARD_LVCMOS18>;
655 pinctrl_usb0_default: usb0-default {
657 groups = "usb0_0_grp";
662 groups = "usb0_0_grp";
663 slew-rate = <SLEW_RATE_SLOW>;
664 io-standard = <IO_STANDARD_LVCMOS18>;
668 pins = "MIO52", "MIO53", "MIO55";
673 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
674 "MIO60", "MIO61", "MIO62", "MIO63";
679 pinctrl_gem3_default: gem3-default {
681 function = "ethernet3";
682 groups = "ethernet3_0_grp";
686 groups = "ethernet3_0_grp";
687 slew-rate = <SLEW_RATE_SLOW>;
688 io-standard = <IO_STANDARD_LVCMOS18>;
692 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
699 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
707 groups = "mdio3_0_grp";
711 groups = "mdio3_0_grp";
712 slew-rate = <SLEW_RATE_SLOW>;
713 io-standard = <IO_STANDARD_LVCMOS18>;
718 pinctrl_can1_default: can1-default {
721 groups = "can1_6_grp";
725 groups = "can1_6_grp";
726 slew-rate = <SLEW_RATE_SLOW>;
727 io-standard = <IO_STANDARD_LVCMOS18>;
741 pinctrl_sdhci1_default: sdhci1-default {
743 groups = "sdio1_0_grp";
748 groups = "sdio1_0_grp";
749 slew-rate = <SLEW_RATE_SLOW>;
750 io-standard = <IO_STANDARD_LVCMOS18>;
755 groups = "sdio1_0_cd_grp";
756 function = "sdio1_cd";
760 groups = "sdio1_0_cd_grp";
763 slew-rate = <SLEW_RATE_SLOW>;
764 io-standard = <IO_STANDARD_LVCMOS18>;
768 groups = "sdio1_0_wp_grp";
769 function = "sdio1_wp";
773 groups = "sdio1_0_wp_grp";
776 slew-rate = <SLEW_RATE_SLOW>;
777 io-standard = <IO_STANDARD_LVCMOS18>;
781 pinctrl_gpio_default: gpio-default {
784 groups = "gpio0_22_grp", "gpio0_23_grp";
788 groups = "gpio0_22_grp", "gpio0_23_grp";
789 slew-rate = <SLEW_RATE_SLOW>;
790 io-standard = <IO_STANDARD_LVCMOS18>;
795 groups = "gpio0_13_grp", "gpio0_38_grp";
799 groups = "gpio0_13_grp", "gpio0_38_grp";
800 slew-rate = <SLEW_RATE_SLOW>;
801 io-standard = <IO_STANDARD_LVCMOS18>;
805 pins = "MIO22", "MIO23";
810 pins = "MIO13", "MIO38";
824 compatible = "m25p80"; /* 32MB */
825 #address-cells = <1>;
828 spi-tx-bus-width = <1>;
829 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
830 spi-max-frequency = <108000000>; /* Based on DC1 spec */
831 partition@qspi-fsbl-uboot { /* for testing purpose */
832 label = "qspi-fsbl-uboot";
833 reg = <0x0 0x100000>;
835 partition@qspi-linux { /* for testing purpose */
836 label = "qspi-linux";
837 reg = <0x100000 0x500000>;
839 partition@qspi-device-tree { /* for testing purpose */
840 label = "qspi-device-tree";
841 reg = <0x600000 0x20000>;
843 partition@qspi-rootfs { /* for testing purpose */
844 label = "qspi-rootfs";
845 reg = <0x620000 0x5E0000>;
856 /* SATA OOB timing settings */
857 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
858 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
859 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
860 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
861 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
862 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
863 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
864 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
865 phy-names = "sata-phy";
866 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
869 /* SD1 with level shifter */
872 pinctrl-names = "default";
873 pinctrl-0 = <&pinctrl_sdhci1_default>;
874 no-1-8-v; /* for 1.0 silicon */
884 pinctrl-names = "default";
885 pinctrl-0 = <&pinctrl_uart0_default>;
890 pinctrl-names = "default";
891 pinctrl-0 = <&pinctrl_uart1_default>;
894 /* ULPI SMSC USB3320 */
897 pinctrl-names = "default";
898 pinctrl-0 = <&pinctrl_usb0_default>;
904 snps,usb3_lpm_capable;
905 phy-names = "usb3-phy";
906 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
907 maximum-speed = "super-speed";
952 &xlnx_dp_snd_codec0 {