2 * Copyright 2015, Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
10 #include <linux/kconfig.h>
11 #include <fsl_ddrc_version.h>
13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
16 * Reserve secure memory
17 * To be aligned with MMU block size
19 #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
22 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
23 #define SRDS_MAX_LANES 8
24 #define CONFIG_SYS_PAGE_SIZE 0x10000
25 #ifndef L1_CACHE_BYTES
26 #define L1_CACHE_SHIFT 6
27 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
28 #define CONFIG_FSL_TZASC_400
31 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
32 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
35 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
36 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
38 #define CONFIG_SYS_FSL_CCSR_GUR_LE
39 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
40 #define CONFIG_SYS_FSL_ESDHC_LE
41 #define CONFIG_SYS_FSL_IFC_LE
42 #define CONFIG_SYS_FSL_PEX_LUT_LE
44 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
46 /* Generic Interrupt Controller Definitions */
47 #define GICD_BASE 0x06000000
48 #define GICR_BASE 0x06100000
51 #define SMMU_BASE 0x05000000 /* GR0 Base */
54 #define CONFIG_SYS_FSL_SFP_VER_3_4
55 #define CONFIG_SYS_FSL_SFP_LE
56 #define CONFIG_SYS_FSL_SRK_LE
58 /* Security Monitor */
59 #define CONFIG_SYS_FSL_SEC_MON_LE
62 #define CONFIG_ESBC_HDR_LS
65 #define CONFIG_SYS_FSL_CCSR_GUR_LE
67 /* Cache Coherent Interconnect */
68 #define CCI_MN_BASE 0x04000000
69 #define CCI_MN_RNF_NODEID_LIST 0x180
70 #define CCI_MN_DVM_DOMAIN_CTL 0x200
71 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
73 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
74 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
75 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
76 #define CCN_HN_F_SAM_NODEID_MASK 0x7f
77 #define CCN_HN_F_SAM_NODEID_DDR0 0x4
78 #define CCN_HN_F_SAM_NODEID_DDR1 0xe
80 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
81 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
82 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
83 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
84 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
85 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
87 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
88 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
89 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
91 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
93 /* TZ Protection Controller Definitions */
94 #define TZPC_BASE 0x02200000
95 #define TZPCR0SIZE_BASE (TZPC_BASE)
96 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
97 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
98 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
99 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
100 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
101 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
102 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
103 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
104 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
106 #define DCSR_CGACRE5 0x700070914ULL
107 #define EPU_EPCMPR5 0x700060914ULL
108 #define EPU_EPCCR5 0x700060814ULL
109 #define EPU_EPSMCR5 0x700060228ULL
110 #define EPU_EPECR5 0x700060314ULL
111 #define EPU_EPCTR5 0x700060a14ULL
112 #define EPU_EPGCR 0x700060000ULL
114 #define CONFIG_SYS_FSL_ERRATUM_A008336
115 #define CONFIG_SYS_FSL_ERRATUM_A008511
116 #define CONFIG_SYS_FSL_ERRATUM_A008514
117 #define CONFIG_SYS_FSL_ERRATUM_A008585
118 #define CONFIG_SYS_FSL_ERRATUM_A008751
119 #define CONFIG_SYS_FSL_ERRATUM_A009635
120 #define CONFIG_SYS_FSL_ERRATUM_A009663
121 #define CONFIG_SYS_FSL_ERRATUM_A009801
122 #define CONFIG_SYS_FSL_ERRATUM_A009803
123 #define CONFIG_SYS_FSL_ERRATUM_A009942
124 #define CONFIG_SYS_FSL_ERRATUM_A010165
126 /* ARM A57 CORE ERRATA */
127 #define CONFIG_ARM_ERRATA_826974
128 #define CONFIG_ARM_ERRATA_828024
129 #define CONFIG_ARM_ERRATA_829520
130 #define CONFIG_ARM_ERRATA_833471
132 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
133 #elif defined(CONFIG_FSL_LSCH2)
134 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
135 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
137 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
138 #define CONFIG_SYS_FSL_ESDHC_BE
139 #define CONFIG_SYS_FSL_WDOG_BE
140 #define CONFIG_SYS_FSL_DSPI_BE
141 #define CONFIG_SYS_FSL_QSPI_BE
142 #define CONFIG_SYS_FSL_CCSR_GUR_BE
143 #define CONFIG_SYS_FSL_PEX_LUT_BE
146 #ifdef CONFIG_LS1043A
147 #define CONFIG_SYS_FMAN_V3
148 #define CONFIG_SYS_NUM_FMAN 1
149 #define CONFIG_SYS_NUM_FM1_DTSEC 7
150 #define CONFIG_SYS_NUM_FM1_10GEC 1
151 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
152 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
154 #define QE_MURAM_SIZE 0x6000UL
155 #define MAX_QE_RISC 1
156 #define QE_NUM_OF_SNUM 28
158 #define CONFIG_SYS_FSL_IFC_BE
159 #define CONFIG_SYS_FSL_SFP_VER_3_2
160 #define CONFIG_SYS_FSL_SEC_MON_BE
161 #define CONFIG_SYS_FSL_SFP_BE
162 #define CONFIG_SYS_FSL_SRK_LE
163 #define CONFIG_KEY_REVOCATION
165 /* SMMU Defintions */
166 #define SMMU_BASE 0x09000000
168 /* Generic Interrupt Controller Definitions */
169 #define GICD_BASE 0x01401000
170 #define GICC_BASE 0x01402000
172 #define CONFIG_SYS_FSL_ERRATUM_A008850
173 #define CONFIG_SYS_FSL_ERRATUM_A009663
174 #define CONFIG_SYS_FSL_ERRATUM_A009929
175 #define CONFIG_SYS_FSL_ERRATUM_A009942
176 #define CONFIG_SYS_FSL_ERRATUM_A009660
177 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
178 #elif defined(CONFIG_ARCH_LS1012A)
179 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
181 #define GICD_BASE 0x01401000
182 #define GICC_BASE 0x01402000
183 #elif defined(CONFIG_ARCH_LS1046A)
184 #define CONFIG_SYS_FMAN_V3
185 #define CONFIG_SYS_NUM_FMAN 1
186 #define CONFIG_SYS_NUM_FM1_DTSEC 8
187 #define CONFIG_SYS_NUM_FM1_10GEC 2
188 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
189 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
191 #define CONFIG_SYS_FSL_IFC_BE
192 #define CONFIG_SYS_FSL_SFP_VER_3_2
193 #define CONFIG_SYS_FSL_SNVS_LE
194 #define CONFIG_SYS_FSL_SFP_BE
195 #define CONFIG_SYS_FSL_SRK_LE
196 #define CONFIG_KEY_REVOCATION
198 /* SMMU Defintions */
199 #define SMMU_BASE 0x09000000
201 /* Generic Interrupt Controller Definitions */
202 #define GICD_BASE 0x01410000
203 #define GICC_BASE 0x01420000
205 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
207 #define CONFIG_SYS_FSL_ERRATUM_A008511
208 #define CONFIG_SYS_FSL_ERRATUM_A009801
209 #define CONFIG_SYS_FSL_ERRATUM_A009803
210 #define CONFIG_SYS_FSL_ERRATUM_A009942
211 #define CONFIG_SYS_FSL_ERRATUM_A010165
213 #error SoC not defined
217 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */