2 * Copyright 2015, Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
10 #include <linux/kconfig.h>
11 #include <fsl_ddrc_version.h>
13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
15 #ifdef CONFIG_SYS_FSL_DDR4
16 #define CONFIG_SYS_FSL_DDRC_GEN4
18 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
21 #ifndef CONFIG_ARCH_LS1012A
22 #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
23 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
27 * Reserve secure memory
28 * To be aligned with MMU block size
30 #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
33 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
34 #define SRDS_MAX_LANES 8
35 #define CONFIG_SYS_PAGE_SIZE 0x10000
36 #ifndef L1_CACHE_BYTES
37 #define L1_CACHE_SHIFT 6
38 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
41 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
42 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
45 #define CONFIG_SYS_FSL_DDR_LE
46 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
47 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
49 #define CONFIG_SYS_FSL_CCSR_GUR_LE
50 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
51 #define CONFIG_SYS_FSL_ESDHC_LE
52 #define CONFIG_SYS_FSL_IFC_LE
53 #define CONFIG_SYS_FSL_PEX_LUT_LE
55 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
57 /* Generic Interrupt Controller Definitions */
58 #define GICD_BASE 0x06000000
59 #define GICR_BASE 0x06100000
62 #define SMMU_BASE 0x05000000 /* GR0 Base */
65 #define CONFIG_SYS_FSL_SFP_VER_3_4
66 #define CONFIG_SYS_FSL_SFP_LE
67 #define CONFIG_SYS_FSL_SRK_LE
70 #define CONFIG_SYS_FSL_SEC_LE
71 #define CONFIG_SYS_FSL_SEC_COMPAT 5
73 /* Security Monitor */
74 #define CONFIG_SYS_FSL_SEC_MON_LE
77 #define CONFIG_ESBC_HDR_LS
80 #define CONFIG_SYS_FSL_CCSR_GUR_LE
82 /* Cache Coherent Interconnect */
83 #define CCI_MN_BASE 0x04000000
84 #define CCI_MN_RNF_NODEID_LIST 0x180
85 #define CCI_MN_DVM_DOMAIN_CTL 0x200
86 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
88 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
89 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
90 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
91 #define CCN_HN_F_SAM_NODEID_MASK 0x7f
92 #define CCN_HN_F_SAM_NODEID_DDR0 0x4
93 #define CCN_HN_F_SAM_NODEID_DDR1 0xe
95 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
96 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
97 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
98 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
99 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
100 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
102 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
103 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
104 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
106 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
108 /* TZ Protection Controller Definitions */
109 #define TZPC_BASE 0x02200000
110 #define TZPCR0SIZE_BASE (TZPC_BASE)
111 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
112 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
113 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
114 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
115 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
116 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
117 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
118 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
119 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
121 #define DCSR_CGACRE5 0x700070914ULL
122 #define EPU_EPCMPR5 0x700060914ULL
123 #define EPU_EPCCR5 0x700060814ULL
124 #define EPU_EPSMCR5 0x700060228ULL
125 #define EPU_EPECR5 0x700060314ULL
126 #define EPU_EPCTR5 0x700060a14ULL
127 #define EPU_EPGCR 0x700060000ULL
129 #define CONFIG_SYS_FSL_ERRATUM_A008336
130 #define CONFIG_SYS_FSL_ERRATUM_A008511
131 #define CONFIG_SYS_FSL_ERRATUM_A008514
132 #define CONFIG_SYS_FSL_ERRATUM_A008585
133 #define CONFIG_SYS_FSL_ERRATUM_A008751
134 #define CONFIG_SYS_FSL_ERRATUM_A009635
135 #define CONFIG_SYS_FSL_ERRATUM_A009663
136 #define CONFIG_SYS_FSL_ERRATUM_A009801
137 #define CONFIG_SYS_FSL_ERRATUM_A009803
138 #define CONFIG_SYS_FSL_ERRATUM_A009942
139 #define CONFIG_SYS_FSL_ERRATUM_A010165
141 /* ARM A57 CORE ERRATA */
142 #define CONFIG_ARM_ERRATA_826974
143 #define CONFIG_ARM_ERRATA_828024
144 #define CONFIG_ARM_ERRATA_829520
145 #define CONFIG_ARM_ERRATA_833471
147 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
148 #elif defined(CONFIG_FSL_LSCH2)
149 #define CONFIG_SYS_FSL_SEC_COMPAT 5
150 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
151 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
152 #define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
154 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
155 #define CONFIG_SYS_FSL_ESDHC_BE
156 #define CONFIG_SYS_FSL_WDOG_BE
157 #define CONFIG_SYS_FSL_DSPI_BE
158 #define CONFIG_SYS_FSL_QSPI_BE
159 #define CONFIG_SYS_FSL_CCSR_GUR_BE
160 #define CONFIG_SYS_FSL_PEX_LUT_BE
161 #define CONFIG_SYS_FSL_SEC_BE
164 #ifdef CONFIG_LS1043A
165 #define CONFIG_SYS_FMAN_V3
166 #define CONFIG_SYS_NUM_FMAN 1
167 #define CONFIG_SYS_NUM_FM1_DTSEC 7
168 #define CONFIG_SYS_NUM_FM1_10GEC 1
169 #define CONFIG_SYS_FSL_DDR_BE
170 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
171 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
173 #define QE_MURAM_SIZE 0x6000UL
174 #define MAX_QE_RISC 1
175 #define QE_NUM_OF_SNUM 28
177 #define CONFIG_SYS_FSL_IFC_BE
178 #define CONFIG_SYS_FSL_SFP_VER_3_2
179 #define CONFIG_SYS_FSL_SEC_MON_BE
180 #define CONFIG_SYS_FSL_SFP_BE
181 #define CONFIG_SYS_FSL_SRK_LE
182 #define CONFIG_KEY_REVOCATION
184 /* SMMU Defintions */
185 #define SMMU_BASE 0x09000000
187 /* Generic Interrupt Controller Definitions */
188 #define GICD_BASE 0x01401000
189 #define GICC_BASE 0x01402000
191 #define CONFIG_SYS_FSL_ERRATUM_A008850
192 #define CONFIG_SYS_FSL_ERRATUM_A009663
193 #define CONFIG_SYS_FSL_ERRATUM_A009929
194 #define CONFIG_SYS_FSL_ERRATUM_A009942
195 #define CONFIG_SYS_FSL_ERRATUM_A009660
196 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
197 #elif defined(CONFIG_ARCH_LS1012A)
198 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
200 #define GICD_BASE 0x01401000
201 #define GICC_BASE 0x01402000
202 #elif defined(CONFIG_ARCH_LS1046A)
203 #define CONFIG_SYS_FMAN_V3
204 #define CONFIG_SYS_NUM_FMAN 1
205 #define CONFIG_SYS_NUM_FM1_DTSEC 8
206 #define CONFIG_SYS_NUM_FM1_10GEC 2
207 #define CONFIG_SYS_FSL_DDR_BE
208 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
209 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
211 #define CONFIG_SYS_FSL_IFC_BE
212 #define CONFIG_SYS_FSL_SFP_VER_3_2
213 #define CONFIG_SYS_FSL_SNVS_LE
214 #define CONFIG_SYS_FSL_SFP_BE
215 #define CONFIG_SYS_FSL_SRK_LE
216 #define CONFIG_KEY_REVOCATION
218 /* SMMU Defintions */
219 #define SMMU_BASE 0x09000000
221 /* Generic Interrupt Controller Definitions */
222 #define GICD_BASE 0x01410000
223 #define GICC_BASE 0x01420000
225 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
227 #define CONFIG_SYS_FSL_ERRATUM_A008511
228 #define CONFIG_SYS_FSL_ERRATUM_A009801
229 #define CONFIG_SYS_FSL_ERRATUM_A009803
230 #define CONFIG_SYS_FSL_ERRATUM_A009942
231 #define CONFIG_SYS_FSL_ERRATUM_A010165
233 #error SoC not defined
237 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */