2 * Copyright 2014-2015, Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _FSL_LAYERSCAPE_CPU_H
8 #define _FSL_LAYERSCAPE_CPU_H
10 static struct cpu_type cpu_type_list[] = {
11 CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
12 CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
13 CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
14 CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
15 CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
16 CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
17 CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
18 CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
19 CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
20 CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
21 CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
22 CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
23 CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
26 #ifndef CONFIG_SYS_DCACHE_OFF
28 #ifdef CONFIG_FSL_LSCH3
29 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
30 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
31 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
32 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
33 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
34 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
35 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
36 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
37 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
38 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
39 #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
40 #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
41 #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
42 #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
43 #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
44 #define CONFIG_SYS_FSL_MC_BASE 0x80c000000
45 #define CONFIG_SYS_FSL_MC_SIZE 0x4000000
46 #define CONFIG_SYS_FSL_NI_BASE 0x810000000
47 #define CONFIG_SYS_FSL_NI_SIZE 0x8000000
48 #define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
49 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
50 #define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
51 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
52 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
53 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
54 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
55 #define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
56 #define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
57 #define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
58 #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
59 #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
60 #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
61 #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
62 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
63 #elif defined(CONFIG_FSL_LSCH2)
64 #define CONFIG_SYS_FSL_BOOTROM_BASE 0x0
65 #define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000
66 #define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
67 #define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
68 #define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
69 #define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
70 #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
71 #define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
72 #define CONFIG_SYS_FSL_IFC_BASE 0x60000000
73 #define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
74 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
75 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
76 #define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000
77 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000
78 #define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000
79 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
80 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000
81 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
82 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
83 #define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000
84 #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
87 #define EARLY_PGTABLE_SIZE 0x5000
88 static struct mm_region early_map[] = {
89 #ifdef CONFIG_FSL_LSCH3
90 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
91 CONFIG_SYS_FSL_CCSR_SIZE,
92 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
93 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
95 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
96 SYS_FSL_OCRAM_SPACE_SIZE,
97 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
99 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
100 CONFIG_SYS_FSL_QSPI_SIZE1,
101 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
102 /* For IFC Region #1, only the first 4MB is cache-enabled */
103 { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
104 CONFIG_SYS_FSL_IFC_SIZE1_1,
105 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
107 { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
108 CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
109 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
110 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
112 { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
113 CONFIG_SYS_FSL_IFC_SIZE1,
114 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
116 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
117 CONFIG_SYS_FSL_DRAM_SIZE1,
118 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
119 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
121 /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
122 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
123 CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
124 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
126 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
127 CONFIG_SYS_FSL_DCSR_SIZE,
128 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
129 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
131 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
132 CONFIG_SYS_FSL_DRAM_SIZE2,
133 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
134 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
136 #elif defined(CONFIG_FSL_LSCH2)
137 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
138 CONFIG_SYS_FSL_CCSR_SIZE,
139 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
140 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
142 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
143 SYS_FSL_OCRAM_SPACE_SIZE,
144 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
146 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
147 CONFIG_SYS_FSL_DCSR_SIZE,
148 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
149 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
151 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
152 CONFIG_SYS_FSL_QSPI_SIZE,
153 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
155 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
156 CONFIG_SYS_FSL_IFC_SIZE,
157 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
159 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
160 CONFIG_SYS_FSL_DRAM_SIZE1,
161 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
162 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
164 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
165 CONFIG_SYS_FSL_DRAM_SIZE2,
166 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
167 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
170 {}, /* list terminator */
173 static struct mm_region final_map[] = {
174 #ifdef CONFIG_FSL_LSCH3
175 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
176 CONFIG_SYS_FSL_CCSR_SIZE,
177 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
178 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
180 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
181 SYS_FSL_OCRAM_SPACE_SIZE,
182 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
184 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
185 CONFIG_SYS_FSL_DRAM_SIZE1,
186 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
187 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
189 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
190 CONFIG_SYS_FSL_QSPI_SIZE1,
191 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
193 { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
194 CONFIG_SYS_FSL_QSPI_SIZE2,
195 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
196 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
198 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
199 CONFIG_SYS_FSL_IFC_SIZE2,
200 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
202 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
203 CONFIG_SYS_FSL_DCSR_SIZE,
204 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
205 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
207 { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
208 CONFIG_SYS_FSL_MC_SIZE,
209 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
210 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
212 { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
213 CONFIG_SYS_FSL_NI_SIZE,
214 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
215 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
217 /* For QBMAN portal, only the first 64MB is cache-enabled */
218 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
219 CONFIG_SYS_FSL_QBMAN_SIZE_1,
220 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
221 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
223 { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
224 CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
225 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
226 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
227 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
229 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
230 CONFIG_SYS_PCIE1_PHYS_SIZE,
231 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
232 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
234 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
235 CONFIG_SYS_PCIE2_PHYS_SIZE,
236 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
237 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
239 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
240 CONFIG_SYS_PCIE3_PHYS_SIZE,
241 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
242 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
244 #ifdef CONFIG_LS2080A
245 { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
246 CONFIG_SYS_PCIE4_PHYS_SIZE,
247 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
248 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
251 { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
252 CONFIG_SYS_FSL_WRIOP1_SIZE,
253 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
254 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
256 { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
257 CONFIG_SYS_FSL_AIOP1_SIZE,
258 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
259 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
261 { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
262 CONFIG_SYS_FSL_PEBUF_SIZE,
263 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
264 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
266 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
267 CONFIG_SYS_FSL_DRAM_SIZE2,
268 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
269 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
271 #elif defined(CONFIG_FSL_LSCH2)
272 { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
273 CONFIG_SYS_FSL_BOOTROM_SIZE,
274 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
275 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
277 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
278 CONFIG_SYS_FSL_CCSR_SIZE,
279 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
280 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
282 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
283 SYS_FSL_OCRAM_SPACE_SIZE,
284 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
286 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
287 CONFIG_SYS_FSL_DCSR_SIZE,
288 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
289 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
291 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
292 CONFIG_SYS_FSL_QSPI_SIZE,
293 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
294 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
296 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
297 CONFIG_SYS_FSL_IFC_SIZE,
298 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
300 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
301 CONFIG_SYS_FSL_DRAM_SIZE1,
302 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
303 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
305 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
306 CONFIG_SYS_FSL_QBMAN_SIZE,
307 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
308 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
310 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
311 CONFIG_SYS_FSL_DRAM_SIZE2,
312 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
313 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
315 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
316 CONFIG_SYS_PCIE1_PHYS_SIZE,
317 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
318 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
320 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
321 CONFIG_SYS_PCIE2_PHYS_SIZE,
322 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
323 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
325 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
326 CONFIG_SYS_PCIE3_PHYS_SIZE,
327 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
328 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
330 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
331 CONFIG_SYS_FSL_DRAM_SIZE3,
332 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
333 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
336 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
337 {}, /* space holder for secure mem */
341 #endif /* !CONFIG_SYS_DCACHE_OFF */
343 int fsl_qoriq_core_to_cluster(unsigned int core);
345 #endif /* _FSL_LAYERSCAPE_CPU_H */