2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ASM_ARCH_LS102XA_IMMAP_H_
8 #define __ASM_ARCH_LS102XA_IMMAP_H_
10 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
11 #define SVR_MIN(svr) (((svr) >> 0) & 0xf)
12 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff)
13 #define IS_E_PROCESSOR(svr) (svr & 0x80000)
15 #define SOC_VER_SLS1020 0x00
16 #define SOC_VER_LS1020 0x10
17 #define SOC_VER_LS1021 0x11
18 #define SOC_VER_LS1022 0x12
20 #define SOC_MAJOR_VER_1_0 0x1
21 #define SOC_MAJOR_VER_2_0 0x2
23 #define CCSR_BRR_OFFSET 0xe4
24 #define CCSR_SCRATCHRW1_OFFSET 0x200
26 #define RCWSR0_SYS_PLL_RAT_SHIFT 25
27 #define RCWSR0_SYS_PLL_RAT_MASK 0x1f
28 #define RCWSR0_MEM_PLL_RAT_SHIFT 16
29 #define RCWSR0_MEM_PLL_RAT_MASK 0x3f
31 #define RCWSR4_SRDS1_PRTCL_SHIFT 24
32 #define RCWSR4_SRDS1_PRTCL_MASK 0xff000000
34 #define TIMER_COMP_VAL 0xffffffff
35 #define ARCH_TIMER_CTRL_ENABLE (1 << 0)
36 #define SYS_COUNTER_CTRL_ENABLE (1 << 24)
38 #define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000
39 #define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000
41 #define DCFG_DCSR_PORCR1 0
44 * Define default values for some CCSR macros to make header files cleaner
46 * To completely disable CCSR relocation in a board header file, define
47 * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
48 * to a value that is the same as CONFIG_SYS_CCSRBAR.
51 #ifdef CONFIG_SYS_CCSRBAR_PHYS
52 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly."
55 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
56 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
57 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW
58 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
61 #ifndef CONFIG_SYS_CCSRBAR
62 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR
65 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
66 #ifdef CONFIG_PHYS_64BIT
67 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
69 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
73 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
74 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR
77 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
78 CONFIG_SYS_CCSRBAR_PHYS_LOW)
81 unsigned long freq_processor[CONFIG_MAX_CPUS];
82 unsigned long freq_systembus;
83 unsigned long freq_ddrbus;
84 unsigned long freq_localbus;
87 /* Device Configuration and Pin Control */
89 u32 porsr1; /* POR status 1 */
90 u32 porsr2; /* POR status 2 */
92 u32 gpporcr1; /* General-purpose POR configuration */
94 u32 dcfg_fusesr; /* Fuse status register */
95 u8 res_02c[0x70-0x2c];
96 u32 devdisr; /* Device disable control */
97 u32 devdisr2; /* Device disable control 2 */
98 u32 devdisr3; /* Device disable control 3 */
99 u32 devdisr4; /* Device disable control 4 */
100 u32 devdisr5; /* Device disable control 5 */
101 u8 res_084[0x94-0x84];
102 u32 coredisru; /* uppper portion for support of 64 cores */
103 u32 coredisrl; /* lower portion for support of 64 cores */
104 u8 res_09c[0xa4-0x9c];
105 u32 svr; /* System version */
106 u8 res_0a8[0xb0-0xa8];
107 u32 rstcr; /* Reset control */
108 u32 rstrqpblsr; /* Reset request preboot loader status */
109 u8 res_0b8[0xc0-0xb8];
110 u32 rstrqmr1; /* Reset request mask */
111 u8 res_0c4[0xc8-0xc4];
112 u32 rstrqsr1; /* Reset request status */
113 u8 res_0cc[0xd4-0xcc];
114 u32 rstrqwdtmrl; /* Reset request WDT mask */
115 u8 res_0d8[0xdc-0xd8];
116 u32 rstrqwdtsrl; /* Reset request WDT status */
117 u8 res_0e0[0xe4-0xe0];
118 u32 brrl; /* Boot release */
119 u8 res_0e8[0x100-0xe8];
120 u32 rcwsr[16]; /* Reset control word status */
121 u8 res_140[0x200-0x140];
122 u32 scratchrw[4]; /* Scratch Read/Write */
123 u8 res_210[0x300-0x210];
124 u32 scratchw1r[4]; /* Scratch Read (Write once) */
125 u8 res_310[0x400-0x310];
127 u8 res_404[0x550-0x404];
129 u8 res_554[0x604-0x554];
132 u8 res_60c[0x740-0x60c]; /* add more registers when needed */
133 u32 tp_ityp[64]; /* Topology Initiator Type Register */
137 } tp_cluster[1]; /* Core Cluster n Topology Register */
138 u8 res_848[0xe60-0x848];
140 u8 res_e60[0xe68-0xe64];
142 u8 res_e68[0xe80-0xe6c];
146 #define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
147 #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
148 #define SCFG_ETSECCMCR_GE0_CLK125 0x00000000
149 #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000
150 #define SCFG_PIXCLKCR_PXCKEN 0x80000000
151 #define SCFG_QSPI_CLKSEL 0xc0100000
153 /* Supplemental Configuration Unit */
169 u32 pex1rdmsgpldlsbsr;
170 u32 pex1rdmsgpldmsbsr;
171 u32 pex2rdmsgpldlsbsr;
172 u32 pex2rdmsgpldmsbsr;
239 u32 clkcncsr; /* core cluster n clock control status */
242 u8 res_040[0x7c0]; /* 0x100 */
248 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */
250 u32 pllpgsr; /* 0xc00 Platform PLL General Status */
252 u32 plldgsr; /* 0xc20 DDR PLL General Status */
270 #define SRDS_MAX_LANES 4
271 #define SRDS_MAX_BANK 2
273 #define SRDS_RSTCTL_RST 0x80000000
274 #define SRDS_RSTCTL_RSTDONE 0x40000000
275 #define SRDS_RSTCTL_RSTERR 0x20000000
276 #define SRDS_RSTCTL_SWRST 0x10000000
277 #define SRDS_RSTCTL_SDEN 0x00000020
278 #define SRDS_RSTCTL_SDRST_B 0x00000040
279 #define SRDS_RSTCTL_PLLRST_B 0x00000080
280 #define SRDS_PLLCR0_POFF 0x80000000
281 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
282 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
283 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
284 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
285 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
286 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
287 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
288 #define SRDS_PLLCR0_PLL_LCK 0x00800000
289 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
290 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
291 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
292 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
293 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
294 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
295 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
296 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
300 u32 rstctl; /* Reset Control Register */
302 u32 pllcr0; /* PLL Control Register 0 */
304 u32 pllcr1; /* PLL Control Register 1 */
305 u32 res_0c; /* 0x00c */
308 u8 res_18[0x20-0x18];
310 u8 res_40[0x90-0x40];
311 u32 srdstcalcr; /* 0x90 TX Calibration Control */
312 u8 res_94[0xa0-0x94];
313 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
314 u8 res_a4[0xb0-0xa4];
315 u32 srdsgr0; /* 0xb0 General Register 0 */
316 u8 res_b4[0xe0-0xb4];
317 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
318 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
319 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
320 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
321 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
322 u8 res_f4[0x100-0xf4];
324 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
325 u8 res_104[0x120-0x104];
327 u8 res_180[0x300-0x180];
329 u32 srdspexeqpcr[11];
330 u8 res_330[0x400-0x330];
332 u8 res_404[0x440-0x404];
334 u8 res_444[0x800-0x444];
336 u32 gcr0; /* 0x800 General Control Register 0 */
337 u32 gcr1; /* 0x804 General Control Register 1 */
338 u32 gcr2; /* 0x808 General Control Register 2 */
340 u32 recr0; /* 0x810 Receive Equalization Control */
342 u32 tecr0; /* 0x818 Transmit Equalization Control */
344 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
345 u8 res_824[0x83c-0x824];
347 } lane[4]; /* Lane A, B, C, D, E, F, G, H */
348 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
351 #define CCI400_CTRLORD_TERM_BARRIER 0x00000008
352 #define CCI400_CTRLORD_EN_BARRIER 0
353 #define CCI400_SHAORD_NON_SHAREABLE 0x00000002
354 #define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
355 #define CCI400_SNOOP_REQ_EN 0x00000001
357 /* CCI-400 registers */
359 u32 ctrl_ord; /* Control Override */
360 u32 spec_ctrl; /* Speculation Control */
361 u32 secure_access; /* Secure Access */
362 u32 status; /* Status */
363 u32 impr_err; /* Imprecise Error */
364 u8 res_14[0x100 - 0x14];
365 u32 pmcr; /* Performance Monitor Control */
366 u8 res_104[0xfd0 - 0x104];
367 u32 pid[8]; /* Peripheral ID */
368 u32 cid[4]; /* Component ID */
370 u32 snoop_ctrl; /* Snoop Control */
371 u32 sha_ord; /* Shareable Override */
372 u8 res_1008[0x1100 - 0x1008];
373 u32 rc_qos_ord; /* read channel QoS Value Override */
374 u32 wc_qos_ord; /* read channel QoS Value Override */
375 u8 res_1108[0x110c - 0x1108];
376 u32 qos_ctrl; /* QoS Control */
377 u32 max_ot; /* Max OT */
378 u8 res_1114[0x1130 - 0x1114];
379 u32 target_lat; /* Target Latency */
380 u32 latency_regu; /* Latency Regulation */
381 u32 qos_range; /* QoS Range */
382 u8 res_113c[0x2000 - 0x113c];
383 } slave[5]; /* Slave Interface */
384 u8 res_6000[0x9004 - 0x6000];
385 u32 cycle_counter; /* Cycle counter */
386 u32 count_ctrl; /* Count Control */
387 u32 overflow_status; /* Overflow Flag Status */
388 u8 res_9010[0xa000 - 0x9010];
390 u32 event_select; /* Event Select */
391 u32 event_count; /* Event Count */
392 u32 counter_ctrl; /* Counter Control */
393 u32 overflow_status; /* Overflow Flag Status */
394 u8 res_a010[0xb000 - 0xa010];
395 } pcounter[4]; /* Performance Counter */
396 u8 res_e004[0x10000 - 0xe004];
398 #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */