2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
21 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
23 #define CCM_CCGR0 0x020C4068
24 #define CCM_CCGR1 0x020C406c
25 #define CCM_CCGR2 0x020C4070
26 #define CCM_CCGR3 0x020C4074
27 #define CCM_CCGR4 0x020C4078
28 #define CCM_CCGR5 0x020C407c
29 #define CCM_CCGR6 0x020C4080
31 #define PMU_MISC2 0x020C8170
39 u32 cacrr; /* 0x0010*/
43 u32 cscmr2; /* 0x0020 */
47 u32 cdcdr; /* 0x0030 */
51 u32 cscdr4; /* 0x0040 */
55 u32 ctor; /* 0x0050 */
59 u32 ccosr; /* 0x0060 */
63 u32 CCGR2; /* 0x0070 */
67 u32 CCGR6; /* 0x0080 */
71 u32 analog_pll_sys; /* 0x4000 */
72 u32 analog_pll_sys_set;
73 u32 analog_pll_sys_clr;
74 u32 analog_pll_sys_tog;
75 u32 analog_usb1_pll_480_ctrl; /* 0x4010 */
76 u32 analog_usb1_pll_480_ctrl_set;
77 u32 analog_usb1_pll_480_ctrl_clr;
78 u32 analog_usb1_pll_480_ctrl_tog;
79 u32 analog_reserved0[4];
80 u32 analog_pll_528; /* 0x4030 */
81 u32 analog_pll_528_set;
82 u32 analog_pll_528_clr;
83 u32 analog_pll_528_tog;
84 u32 analog_pll_528_ss; /* 0x4040 */
85 u32 analog_reserved1[3];
86 u32 analog_pll_528_num; /* 0x4050 */
87 u32 analog_reserved2[3];
88 u32 analog_pll_528_denom; /* 0x4060 */
89 u32 analog_reserved3[3];
90 u32 analog_pll_audio; /* 0x4070 */
91 u32 analog_pll_audio_set;
92 u32 analog_pll_audio_clr;
93 u32 analog_pll_audio_tog;
94 u32 analog_pll_audio_num; /* 0x4080*/
95 u32 analog_reserved4[3];
96 u32 analog_pll_audio_denom; /* 0x4090 */
97 u32 analog_reserved5[3];
98 u32 analog_pll_video; /* 0x40a0 */
99 u32 analog_pll_video_set;
100 u32 analog_pll_video_clr;
101 u32 analog_pll_video_tog;
102 u32 analog_pll_video_num; /* 0x40b0 */
103 u32 analog_reserved6[3];
104 u32 analog_pll_vedio_denon; /* 0x40c0 */
105 u32 analog_reserved7[7];
106 u32 analog_pll_enet; /* 0x40e0 */
107 u32 analog_pll_enet_set;
108 u32 analog_pll_enet_clr;
109 u32 analog_pll_enet_tog;
110 u32 analog_pfd_480; /* 0x40f0 */
111 u32 analog_pfd_480_set;
112 u32 analog_pfd_480_clr;
113 u32 analog_pfd_480_tog;
114 u32 analog_pfd_528; /* 0x4100 */
115 u32 analog_pfd_528_set;
116 u32 analog_pfd_528_clr;
117 u32 analog_pfd_528_tog;
121 /* Define the bits in register CCR */
122 #define MXC_CCM_CCR_RBC_EN (1 << 27)
123 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
124 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
125 #define MXC_CCM_CCR_WB_COUNT_MASK 0x7
126 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
127 #define MXC_CCM_CCR_COSC_EN (1 << 12)
128 #define MXC_CCM_CCR_OSCNT_MASK 0xFF
129 #define MXC_CCM_CCR_OSCNT_OFFSET 0
131 /* Define the bits in register CCDR */
132 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
133 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
135 /* Define the bits in register CSR */
136 #define MXC_CCM_CSR_COSC_READY (1 << 5)
137 #define MXC_CCM_CSR_REF_EN_B (1 << 0)
139 /* Define the bits in register CCSR */
140 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
141 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
142 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
143 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
144 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
145 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
146 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
147 #define MXC_CCM_CCSR_STEP_SEL (1 << 8)
148 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
149 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
150 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
152 /* Define the bits in register CACRR */
153 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
154 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
156 /* Define the bits in register CBCDR */
157 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
158 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
159 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
160 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
161 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
162 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
163 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
164 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
165 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
166 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
167 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
168 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
169 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
170 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
171 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
172 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
173 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
174 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
176 /* Define the bits in register CBCMR */
177 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
178 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
179 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
180 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
181 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
182 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
183 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
184 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
185 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
186 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
187 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
188 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
189 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
190 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
191 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
192 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
193 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
194 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
195 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
196 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
197 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
198 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
199 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
200 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
201 #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
203 /* Define the bits in register CSCMR1 */
204 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
205 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
206 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
207 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
208 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
209 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
210 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
211 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
212 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
213 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
214 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
215 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
216 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
217 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
218 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
219 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
220 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
221 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
222 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
224 /* Define the bits in register CSCMR2 */
225 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
226 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
227 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
228 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
229 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2)
230 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2
232 /* Define the bits in register CSCDR1 */
233 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
234 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
235 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
236 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
237 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
238 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
239 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
240 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
241 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
242 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
243 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
244 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
245 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
246 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
248 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F
249 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
251 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
253 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
255 /* Define the bits in register CS1CDR */
256 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
257 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
258 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
259 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
260 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
261 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
262 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
263 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
264 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F
265 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
267 /* Define the bits in register CS2CDR */
268 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
269 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
270 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
271 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
272 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
273 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
274 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
275 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
276 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
277 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
278 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
279 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
280 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F
281 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
283 /* Define the bits in register CDCDR */
284 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
285 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
286 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
287 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
288 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
289 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19)
290 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19
291 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
292 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
293 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
294 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
295 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
296 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
297 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
298 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
300 /* Define the bits in register CHSCCDR */
301 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
302 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
303 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
304 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
305 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
306 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
307 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
308 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
309 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
310 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
311 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
312 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
314 #define CHSCCDR_CLK_SEL_LDB_DI0 3
315 #define CHSCCDR_PODF_DIVIDE_BY_3 2
316 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
318 /* Define the bits in register CSCDR2 */
319 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
320 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
321 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
322 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
323 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
324 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12
325 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
326 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9
327 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
328 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
329 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
330 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3
331 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7
332 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0
334 /* Define the bits in register CSCDR3 */
335 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
336 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
337 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
338 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
339 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
340 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
341 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
342 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
344 /* Define the bits in register CDHIPR */
345 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
346 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
347 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
348 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
349 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
350 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
351 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1
353 /* Define the bits in register CLPCR */
354 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
355 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
356 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
357 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
358 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
359 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
360 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
361 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
362 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
363 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17)
364 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
365 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
366 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
367 #define MXC_CCM_CLPCR_VSTBY (1 << 8)
368 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
369 #define MXC_CCM_CLPCR_SBYOS (1 << 6)
370 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
371 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
372 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
373 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
374 #define MXC_CCM_CLPCR_LPM_MASK 0x3
375 #define MXC_CCM_CLPCR_LPM_OFFSET 0
377 /* Define the bits in register CISR */
378 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
379 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
380 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
381 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
382 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
383 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
384 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
385 #define MXC_CCM_CISR_COSC_READY (1 << 6)
386 #define MXC_CCM_CISR_LRF_PLL 1
388 /* Define the bits in register CIMR */
389 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
390 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
391 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
392 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
393 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
394 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22)
395 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
396 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
397 #define MXC_CCM_CIMR_MASK_LRF_PLL 1
399 /* Define the bits in register CCOSR */
400 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
401 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
402 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
403 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
404 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
405 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
406 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
407 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
408 #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF
409 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
411 /* Define the bits in registers CGPR */
412 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
413 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
414 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1
416 /* Define the bits in registers CCGRx */
417 #define MXC_CCM_CCGR_CG_MASK 3
419 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
420 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
421 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
422 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
423 #define MXC_CCM_CCGR0_APBHDMA HCLK_OFFSET 4
424 #define MXC_CCM_CCGR0_AMASK (3<<MXC_CCM_CCGR0_APBHDMA)
425 #define MXC_CCM_CCGR0_ASRC_OFFSET 6
426 #define MXC_CCM_CCGR0_ASRC_MASK (3<<MXC_CCM_CCGR0_ASRC_OFFSET)
427 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
428 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3<<MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
429 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
430 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
431 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
432 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
433 #define MXC_CCM_CCGR0_CAN1_OFFSET 14
434 #define MXC_CCM_CCGR0_CAN1_MASK (3<<MXC_CCM_CCGR0_CAN1_OFFSET)
435 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
436 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
437 #define MXC_CCM_CCGR0_CAN2_OFFSET 18
438 #define MXC_CCM_CCGR0_CAN2_MASK (3<<MXC_CCM_CCGR0_CAN2_OFFSET)
439 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
440 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
441 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
442 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3<<MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
443 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24
444 #define MXC_CCM_CCGR0_DCIC1_MASK (3<<MXC_CCM_CCGR0_DCIC1_OFFSET)
445 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26
446 #define MXC_CCM_CCGR0_DCIC2_MASK (3<<MXC_CCM_CCGR0_DCIC2_OFFSET)
447 #define MXC_CCM_CCGR0_DTCP_OFFSET 28
448 #define MXC_CCM_CCGR0_DTCP_MASK (3<<MXC_CCM_CCGR0_DTCP_OFFSET)
450 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
451 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3<<MXC_CCM_CCGR1_ECSPI1S_OFFSET)
452 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
453 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3<<MXC_CCM_CCGR1_ECSPI2S_OFFSET)
454 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
455 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3<<MXC_CCM_CCGR1_ECSPI3S_OFFSET)
456 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
457 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3<<MXC_CCM_CCGR1_ECSPI4S_OFFSET)
458 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
459 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3<<MXC_CCM_CCGR1_ECSPI5S_OFFSET)
460 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
461 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3<<MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
462 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
463 #define MXC_CCM_CCGR1_EPIT1S_MASK (3<<MXC_CCM_CCGR1_EPIT1S_OFFSET)
464 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
465 #define MXC_CCM_CCGR1_EPIT2S_MASK (3<<MXC_CCM_CCGR1_EPIT2S_OFFSET)
466 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16
467 #define MXC_CCM_CCGR1_ESAIS_MASK (3<<MXC_CCM_CCGR1_ESAIS_OFFSET)
468 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
469 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3<<MXC_CCM_CCGR1_GPT_BUS_OFFSET)
470 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
471 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3<<MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
472 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24
473 #define MXC_CCM_CCGR1_GPU2D_MASK (3<<MXC_CCM_CCGR1_GPU2D_OFFSET)
474 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26
475 #define MXC_CCM_CCGR1_GPU3D_MASK (3<<MXC_CCM_CCGR1_GPU3D_OFFSET)
477 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
478 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
479 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
480 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
481 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
482 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
483 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
484 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
485 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
486 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
487 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
488 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3<<MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
489 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
490 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3<<MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
491 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
492 #define MXC_CCM_CCGR2_IPMUX1_MASK (3<<MXC_CCM_CCGR2_IPMUX1_OFFSET)
493 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
494 #define MXC_CCM_CCGR2_IPMUX2_MASK (3<<MXC_CCM_CCGR2_IPMUX2_OFFSET)
495 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
496 #define MXC_CCM_CCGR2_IPMUX3_MASK (3<<MXC_CCM_CCGR2_IPMUX3_OFFSET)
497 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
498 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
499 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
500 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
501 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
502 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3<<MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
504 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
505 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
506 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
507 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
508 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
509 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
510 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
511 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
512 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
513 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
514 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
515 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
516 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
517 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3<<MXC_CCM_CCGR3_LDB_DI0_OFFSET)
518 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
519 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3<<MXC_CCM_CCGR3_LDB_DI1_OFFSET)
520 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
521 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3<<MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
522 #define MXC_CCM_CCGR3_MLB_OFFSET 18
523 #define MXC_CCM_CCGR3_MLB_MASK (3<<MXC_CCM_CCGR3_MLB_OFFSET)
524 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
525 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
526 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
527 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
528 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
529 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
530 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
531 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
532 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28
533 #define MXC_CCM_CCGR3_OCRAM_MASK (3<<MXC_CCM_CCGR3_OCRAM_OFFSET)
534 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
535 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3<<MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
537 #define MXC_CCM_CCGR4_PCIE_OFFSET 0
538 #define MXC_CCM_CCGR4_PCIE_MASK (3<<MXC_CCM_CCGR4_PCIE_OFFSET)
539 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
540 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
541 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
542 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
543 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
544 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
545 #define MXC_CCM_CCGR4_PWM1_OFFSET 16
546 #define MXC_CCM_CCGR4_PWM1_MASK (3<<MXC_CCM_CCGR4_PWM1_OFFSET)
547 #define MXC_CCM_CCGR4_PWM2_OFFSET 18
548 #define MXC_CCM_CCGR4_PWM2_MASK (3<<MXC_CCM_CCGR4_PWM2_OFFSET)
549 #define MXC_CCM_CCGR4_PWM3_OFFSET 20
550 #define MXC_CCM_CCGR4_PWM3_MASK (3<<MXC_CCM_CCGR4_PWM3_OFFSET)
551 #define MXC_CCM_CCGR4_PWM4_OFFSET 22
552 #define MXC_CCM_CCGR4_PWM4_MASK (3<<MXC_CCM_CCGR4_PWM4_OFFSET)
553 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
554 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
555 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
556 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
557 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
558 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
559 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
560 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
562 #define MXC_CCM_CCGR5_ROM_OFFSET 0
563 #define MXC_CCM_CCGR5_ROM_MASK (3<<MXC_CCM_CCGR5_ROM_OFFSET)
564 #define MXC_CCM_CCGR5_SATA_OFFSET 4
565 #define MXC_CCM_CCGR5_SATA_MASK (3<<MXC_CCM_CCGR5_SATA_OFFSET)
566 #define MXC_CCM_CCGR5_SDMA_OFFSET 6
567 #define MXC_CCM_CCGR5_SDMA_MASK (3<<MXC_CCM_CCGR5_SDMA_OFFSET)
568 #define MXC_CCM_CCGR5_SPBA_OFFSET 12
569 #define MXC_CCM_CCGR5_SPBA_MASK (3<<MXC_CCM_CCGR5_SPBA_OFFSET)
570 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14
571 #define MXC_CCM_CCGR5_SPDIF_MASK (3<<MXC_CCM_CCGR5_SPDIF_OFFSET)
572 #define MXC_CCM_CCGR5_SSI1_OFFSET 18
573 #define MXC_CCM_CCGR5_SSI1_MASK (3<<MXC_CCM_CCGR5_SSI1_OFFSET)
574 #define MXC_CCM_CCGR5_SSI2_OFFSET 20
575 #define MXC_CCM_CCGR5_SSI2_MASK (3<<MXC_CCM_CCGR5_SSI2_OFFSET)
576 #define MXC_CCM_CCGR5_SSI3_OFFSET 22
577 #define MXC_CCM_CCGR5_SSI3_MASK (3<<MXC_CCM_CCGR5_SSI3_OFFSET)
578 #define MXC_CCM_CCGR5_UART_OFFSET 24
579 #define MXC_CCM_CCGR5_UART_MASK (3<<MXC_CCM_CCGR5_UART_OFFSET)
580 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
581 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3<<MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
583 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
584 #define MXC_CCM_CCGR6_USBOH3_MASK (3<<MXC_CCM_CCGR6_USBOH3_OFFSET)
585 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2
586 #define MXC_CCM_CCGR6_USDHC1_MASK (3<<MXC_CCM_CCGR6_USDHC1_OFFSET)
587 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4
588 #define MXC_CCM_CCGR6_USDHC2_MASK (3<<MXC_CCM_CCGR6_USDHC2_OFFSET)
589 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6
590 #define MXC_CCM_CCGR6_USDHC3_MASK (3<<MXC_CCM_CCGR6_USDHC3_OFFSET)
591 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8
592 #define MXC_CCM_CCGR6_USDHC4_MASK (3<<MXC_CCM_CCGR6_USDHC4_OFFSET)
593 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
594 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3<<MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
595 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
596 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3<<MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
598 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
599 #define BP_ANADIG_PLL_SYS_RSVD0 20
600 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
601 #define BF_ANADIG_PLL_SYS_RSVD0(v) \
602 (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
603 #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
604 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
605 #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
606 #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
607 #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
608 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
609 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
610 (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
611 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
612 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
613 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
614 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
615 #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
616 #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
617 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
618 #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
619 #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
620 #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
621 #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
622 #define BP_ANADIG_PLL_SYS_DIV_SELECT 0
623 #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
624 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
625 (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
627 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
628 #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17
629 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
630 #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \
631 (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
632 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
633 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
634 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
635 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
636 (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
637 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
638 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
639 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
640 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
641 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
642 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
643 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
644 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
645 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
646 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
647 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
648 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
649 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
650 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
651 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
652 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
653 (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
654 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
655 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
656 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
657 (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
659 #define BM_ANADIG_PLL_528_LOCK 0x80000000
660 #define BP_ANADIG_PLL_528_RSVD1 19
661 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
662 #define BF_ANADIG_PLL_528_RSVD1(v) \
663 (((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
664 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
665 #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
666 #define BM_ANADIG_PLL_528_BYPASS 0x00010000
667 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
668 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
669 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
670 (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
671 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
672 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
673 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
674 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
675 #define BM_ANADIG_PLL_528_ENABLE 0x00002000
676 #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
677 #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
678 #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
679 #define BM_ANADIG_PLL_528_HALF_CP 0x00000200
680 #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
681 #define BM_ANADIG_PLL_528_HALF_LF 0x00000080
682 #define BP_ANADIG_PLL_528_RSVD0 1
683 #define BM_ANADIG_PLL_528_RSVD0 0x0000007E
684 #define BF_ANADIG_PLL_528_RSVD0(v) \
685 (((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
686 #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
688 #define BP_ANADIG_PLL_528_SS_STOP 16
689 #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
690 #define BF_ANADIG_PLL_528_SS_STOP(v) \
691 (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
692 #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
693 #define BP_ANADIG_PLL_528_SS_STEP 0
694 #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
695 #define BF_ANADIG_PLL_528_SS_STEP(v) \
696 (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
698 #define BP_ANADIG_PLL_528_NUM_RSVD0 30
699 #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
700 #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
701 (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
702 #define BP_ANADIG_PLL_528_NUM_A 0
703 #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
704 #define BF_ANADIG_PLL_528_NUM_A(v) \
705 (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
707 #define BP_ANADIG_PLL_528_DENOM_RSVD0 30
708 #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
709 #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
710 (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
711 #define BP_ANADIG_PLL_528_DENOM_B 0
712 #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
713 #define BF_ANADIG_PLL_528_DENOM_B(v) \
714 (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
716 #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
717 #define BP_ANADIG_PLL_AUDIO_RSVD0 22
718 #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
719 #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \
720 (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
721 #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
722 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
723 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
724 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
725 (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
726 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
727 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
728 #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
729 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
730 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
731 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
732 (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
733 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
734 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
735 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
736 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
737 #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
738 #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
739 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
740 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
741 #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
742 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
743 #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
744 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
745 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
746 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
747 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
749 #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30
750 #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
751 #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
752 (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
753 #define BP_ANADIG_PLL_AUDIO_NUM_A 0
754 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
755 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
756 (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
758 #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30
759 #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
760 #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
761 (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
762 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
763 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
764 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
765 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
767 #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
768 #define BP_ANADIG_PLL_VIDEO_RSVD0 22
769 #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
770 #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
771 (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
772 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
773 #define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
774 #define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
775 #define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
776 (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
777 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
778 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
779 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
780 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
781 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
782 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
783 (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
784 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
785 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
786 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
787 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
788 #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
789 #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
790 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
791 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
792 #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
793 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
794 #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
795 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
796 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
797 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
798 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
800 #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30
801 #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
802 #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
803 (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
804 #define BP_ANADIG_PLL_VIDEO_NUM_A 0
805 #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
806 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
807 (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
809 #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30
810 #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
811 #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
812 (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
813 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
814 #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
815 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
816 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
818 #define BM_ANADIG_PLL_ENET_LOCK 0x80000000
819 #define BP_ANADIG_PLL_ENET_RSVD1 21
820 #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
821 #define BF_ANADIG_PLL_ENET_RSVD1(v) \
822 (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
823 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
824 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
825 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
826 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
827 #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
828 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
829 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
830 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
831 (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
832 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
833 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
834 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
835 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
836 #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
837 #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
838 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
839 #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
840 #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
841 #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
842 #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
843 #define BP_ANADIG_PLL_ENET_RSVD0 2
844 #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
845 #define BF_ANADIG_PLL_ENET_RSVD0(v) \
846 (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
847 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
848 #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
849 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
850 (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
852 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
853 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
854 #define BP_ANADIG_PFD_480_PFD3_FRAC 24
855 #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
856 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
857 (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
858 #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
859 #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
860 #define BP_ANADIG_PFD_480_PFD2_FRAC 16
861 #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
862 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
863 (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
864 #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
865 #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
866 #define BP_ANADIG_PFD_480_PFD1_FRAC 8
867 #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
868 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
869 (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
870 #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
871 #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
872 #define BP_ANADIG_PFD_480_PFD0_FRAC 0
873 #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
874 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
875 (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
877 #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
878 #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
879 #define BP_ANADIG_PFD_528_PFD3_FRAC 24
880 #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
881 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
882 (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
883 #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
884 #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
885 #define BP_ANADIG_PFD_528_PFD2_FRAC 16
886 #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
887 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
888 (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
889 #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
890 #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
891 #define BP_ANADIG_PFD_528_PFD1_FRAC 8
892 #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
893 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
894 (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
895 #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
896 #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
897 #define BP_ANADIG_PFD_528_PFD0_FRAC 0
898 #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
899 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
900 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
902 #define PLL2_PFD0_FREQ 352000000
903 #define PLL2_PFD1_FREQ 594000000
904 #define PLL2_PFD2_FREQ 400000000
905 #define PLL2_PFD2_DIV_FREQ 200000000
906 #define PLL3_PFD0_FREQ 720000000
907 #define PLL3_PFD1_FREQ 540000000
908 #define PLL3_PFD2_FREQ 508200000
909 #define PLL3_PFD3_FREQ 454700000
910 #define PLL3_80M 80000000
911 #define PLL3_60M 60000000
913 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */