2 * Copyright (C) 2013 Boundary Devices Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18 #ifndef __ASM_ARCH_MX6DLS_DDR_H__
19 #define __ASM_ARCH_MX6DLS_DDR_H__
27 #define MX6_IOM_DRAM_DQM0 0x020e0470
28 #define MX6_IOM_DRAM_DQM1 0x020e0474
29 #define MX6_IOM_DRAM_DQM2 0x020e0478
30 #define MX6_IOM_DRAM_DQM3 0x020e047c
31 #define MX6_IOM_DRAM_DQM4 0x020e0480
32 #define MX6_IOM_DRAM_DQM5 0x020e0484
33 #define MX6_IOM_DRAM_DQM6 0x020e0488
34 #define MX6_IOM_DRAM_DQM7 0x020e048c
36 #define MX6_IOM_DRAM_CAS 0x020e0464
37 #define MX6_IOM_DRAM_RAS 0x020e0490
38 #define MX6_IOM_DRAM_RESET 0x020e0494
39 #define MX6_IOM_DRAM_SDCLK_0 0x020e04ac
40 #define MX6_IOM_DRAM_SDCLK_1 0x020e04b0
41 #define MX6_IOM_DRAM_SDBA2 0x020e04a0
42 #define MX6_IOM_DRAM_SDCKE0 0x020e04a4
43 #define MX6_IOM_DRAM_SDCKE1 0x020e04a8
44 #define MX6_IOM_DRAM_SDODT0 0x020e04b4
45 #define MX6_IOM_DRAM_SDODT1 0x020e04b8
47 #define MX6_IOM_DRAM_SDQS0 0x020e04bc
48 #define MX6_IOM_DRAM_SDQS1 0x020e04c0
49 #define MX6_IOM_DRAM_SDQS2 0x020e04c4
50 #define MX6_IOM_DRAM_SDQS3 0x020e04c8
51 #define MX6_IOM_DRAM_SDQS4 0x020e04cc
52 #define MX6_IOM_DRAM_SDQS5 0x020e04d0
53 #define MX6_IOM_DRAM_SDQS6 0x020e04d4
54 #define MX6_IOM_DRAM_SDQS7 0x020e04d8
56 #define MX6_IOM_GRP_B0DS 0x020e0764
57 #define MX6_IOM_GRP_B1DS 0x020e0770
58 #define MX6_IOM_GRP_B2DS 0x020e0778
59 #define MX6_IOM_GRP_B3DS 0x020e077c
60 #define MX6_IOM_GRP_B4DS 0x020e0780
61 #define MX6_IOM_GRP_B5DS 0x020e0784
62 #define MX6_IOM_GRP_B6DS 0x020e078c
63 #define MX6_IOM_GRP_B7DS 0x020e0748
64 #define MX6_IOM_GRP_ADDDS 0x020e074c
65 #define MX6_IOM_DDRMODE_CTL 0x020e0750
66 #define MX6_IOM_GRP_DDRPKE 0x020e0754
67 #define MX6_IOM_GRP_DDRMODE 0x020e0760
68 #define MX6_IOM_GRP_CTLDS 0x020e076c
69 #define MX6_IOM_GRP_DDR_TYPE 0x020e0774
71 #endif /*__ASM_ARCH_MX6S_DDR_H__ */