2 * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ASM_ARCH_MX7_IMX_REGS_H__
8 #define __ASM_ARCH_MX7_IMX_REGS_H__
12 #define CONFIG_SYS_CACHELINE_SIZE 64
14 #define ROM_SW_INFO_ADDR 0x000001E8
15 #define ROMCP_ARB_BASE_ADDR 0x00000000
16 #define ROMCP_ARB_END_ADDR 0x00017FFF
17 #define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR
18 #define CAAM_ARB_BASE_ADDR 0x00100000
19 #define CAAM_ARB_END_ADDR 0x00107FFF
20 #define GIC400_ARB_BASE_ADDR 0x31000000
21 #define GIC400_ARB_END_ADDR 0x31007FFF
22 #define APBH_DMA_ARB_BASE_ADDR 0x33000000
23 #define APBH_DMA_ARB_END_ADDR 0x33007FFF
24 #define M4_BOOTROM_BASE_ADDR 0x00180000
26 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
27 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
28 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
30 /* GPV - PL301 configuration ports */
31 #define GPV0_BASE_ADDR 0x32000000
32 #define GPV1_BASE_ADDR 0x32100000
33 #define GPV2_BASE_ADDR 0x32200000
34 #define GPV3_BASE_ADDR 0x32300000
35 #define GPV4_BASE_ADDR 0x32400000
36 #define GPV5_BASE_ADDR 0x32500000
37 #define GPV6_BASE_ADDR 0x32600000
38 #define GPV7_BASE_ADDR 0x32700000
40 #define OCRAM_ARB_BASE_ADDR 0x00900000
41 #define OCRAM_ARB_END_ADDR 0x0091FFFF
42 #define OCRAM_EPDC_BASE_ADDR 0x00920000
43 #define OCRAM_EPDC_END_ADDR 0x0093FFFF
44 #define OCRAM_PXP_BASE_ADDR 0x00940000
45 #define OCRAM_PXP_END_ADDR 0x00947FFF
46 #define IRAM_BASE_ADDR OCRAM_ARB_BASE_ADDR
47 #define IRAM_SIZE 0x00020000
49 #define AIPS1_ARB_BASE_ADDR 0x30000000
50 #define AIPS1_ARB_END_ADDR 0x303FFFFF
51 #define AIPS2_ARB_BASE_ADDR 0x30400000
52 #define AIPS2_ARB_END_ADDR 0x307FFFFF
53 #define AIPS3_ARB_BASE_ADDR 0x30800000
54 #define AIPS3_ARB_END_ADDR 0x30BFFFFF
56 #define WEIM_ARB_BASE_ADDR 0x28000000
57 #define WEIM_ARB_END_ADDR 0x2FFFFFFF
59 #define QSPI0_ARB_BASE_ADDR 0x60000000
60 #define QSPI0_ARB_END_ADDR 0x6FFFFFFF
61 #define PCIE_ARB_BASE_ADDR 0x40000000
62 #define PCIE_ARB_END_ADDR 0x4FFFFFFF
63 #define PCIE_REG_BASE_ADDR 0x33800000
64 #define PCIE_REG_END_ADDR 0x33803FFF
66 #define MMDC0_ARB_BASE_ADDR 0x80000000
67 #define MMDC0_ARB_END_ADDR 0xBFFFFFFF
68 #define MMDC1_ARB_BASE_ADDR 0xC0000000
69 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
71 /* Cortex-A9 MPCore private memory region */
72 #define ARM_PERIPHBASE 0x31000000
73 #define SCU_BASE_ADDR ARM_PERIPHBASE
74 #define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200)
75 #define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600)
78 /* Defines for Blocks connected via AIPS (SkyBlue) */
79 #define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
80 #define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
81 #define AIPS_TZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR
83 /* DAP base-address */
84 #define ARM_IPS_BASE_ADDR AIPS1_ARB_BASE_ADDR
86 /* AIPS_TZ#1- On Platform */
87 #define AIPS1_ON_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x1F0000)
88 /* AIPS_TZ#1- Off Platform */
89 #define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x200000)
91 #define GPIO1_BASE_ADDR AIPS1_OFF_BASE_ADDR
92 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x10000)
93 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x20000)
94 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x30000)
95 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x40000)
96 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x50000)
97 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x60000)
98 #define IOMUXC_LPSR_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x70000)
99 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x80000)
100 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x90000)
101 #define WDOG3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xA0000)
102 #define WDOG4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xB0000)
103 #define IOMUXC_LPSR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xC0000)
104 #define GPT_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xD0000)
105 #define GPT1_BASE_ADDR GPT_IPS_BASE_ADDR
106 #define GPT2_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xE0000)
107 #define GPT3_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xF0000)
108 #define GPT4_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x100000)
109 #define ROMCP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x110000)
110 #define KPP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x120000)
111 #define IOMUXC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x130000)
112 #define IOMUXC_BASE_ADDR IOMUXC_IPS_BASE_ADDR
113 #define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x140000)
114 #define OCOTP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x150000)
115 #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x160000)
116 #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x170000)
117 #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x180000)
118 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x190000)
119 #define GPC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1A0000)
120 #define SEMA41_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1B0000)
121 #define SEMA42_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1C0000)
122 #define RDC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1D0000)
123 #define CSU_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1E0000)
125 /* AIPS_TZ#2- On Platform */
126 #define AIPS2_ON_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x1F0000)
127 /* AIPS_TZ#2- Off Platform */
128 #define AIPS2_OFF_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x200000)
129 #define ADC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x10000)
130 #define ADC2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x20000)
131 #define ECSPI4_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x30000)
132 #define FTM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x40000)
133 #define FTM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x50000)
134 #define PWM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x60000)
135 #define PWM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x70000)
136 #define PWM3_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x80000)
137 #define PWM4_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x90000)
138 #define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xA0000)
139 #define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xB0000)
140 #define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC0000)
141 #define PCIE_PHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xD0000)
142 #define EPDC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xF0000)
143 #define EPDC_BASE_ADDR EPDC_IPS_BASE_ADDR
144 #define EPXP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x100000)
145 #define CSI1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x110000)
146 #define ELCDIF1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x130000)
147 #define MIPI_CSI2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x150000)
148 #define MIPI_DSI_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x160000)
149 #define IP2APB_TZASC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x180000)
150 #define DDRPHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x190000)
151 #define DDRC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1A0000)
152 #define IP2APB_PERFMON1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1C0000)
153 #define IP2APB_PERFMON2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1D0000)
154 #define IP2APB_AXIMON_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1E0000)
155 #define QOSC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1F0000)
157 /* AIPS_TZ#3 - Global enable (0) */
158 #define ECSPI1_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x20000)
159 #define ECSPI2_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x30000)
160 #define ECSPI3_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x40000)
161 #define UART1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x60000)
162 #define UART3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x80000)
163 #define UART2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x90000)
164 #define SAI1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xA0000)
165 #define SAI2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xB0000)
166 #define SAI3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xC0000)
167 #define SPBA_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xF0000)
168 #define CAAM_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x100000)
170 /* AIPS_TZ#3- On Platform */
171 #define AIPS3_ON_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x1F0000)
172 /* AIPS_TZ#3- Off Platform */
173 #define AIPS3_OFF_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x200000)
174 #define CAN1_IPS_BASE_ADDR AIPS3_OFF_BASE_ADDR
175 #define CAN2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x10000)
176 #define I2C1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x20000)
177 #define I2C2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x30000)
178 #define I2C3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x40000)
179 #define I2C4_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x50000)
180 #define UART4_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x60000)
181 #define UART5_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x70000)
182 #define UART6_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x80000)
183 #define UART7_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x90000)
184 #define MUCPU_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xA0000)
185 #define MUDSP_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xB0000)
186 #define HS_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xC0000)
187 #define USBOH2_PL301_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xD0000)
188 #define USBOTG1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x110000)
189 #define USBOTG2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x120000)
190 #define USBHSIC_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x130000)
191 #define USDHC1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x140000)
192 #define USDHC2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x150000)
193 #define USDHC3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x160000)
194 #define EMVSIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000)
195 #define EMVSIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000)
196 #define SIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000)
197 #define SIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000)
198 #define QSPI1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1B0000)
199 #define WEIM_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1C0000)
200 #define SDMA_PORT_IPS_HOST_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1D0000)
201 #define ENET_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1E0000)
202 #define ENET2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1F0000)
204 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
205 #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
206 #define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
208 #define SDMA_IPS_HOST_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR
209 #define SDMA_IPS_HOST_IPS_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR
211 #define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR
212 #define DEBUG_MONITOR_BASE_ADDR IP2APB_AXIMON_IPS_BASE_ADDR
214 #define USB_BASE_ADDR USBOTG1_IPS_BASE_ADDR
216 #define FEC_QUIRK_ENET_MAC
217 #define SNVS_LPGPR 0x68
219 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
220 #include <asm/types.h>
222 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
224 /* System Reset Controller (SRC) */
259 /* GPR0 Bit Fields */
260 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u
261 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0
262 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u
263 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1
264 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u
265 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2
266 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u
267 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3
268 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u
269 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4
270 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u
271 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5
272 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u
273 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6
274 /* GPR1 Bit Fields */
275 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u
276 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0
277 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK 0x6u
278 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT 1
279 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK)
280 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_MASK 0x8u
281 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_SHIFT 3
282 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK 0x30u
283 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT 4
284 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK)
285 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_MASK 0x40u
286 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_SHIFT 6
287 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK 0x180u
288 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT 7
289 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK)
290 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_MASK 0x200u
291 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_SHIFT 9
292 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK 0xC00u
293 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT 10
294 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK)
295 #define IOMUXC_GPR_GPR1_GPR_IRQ_MASK 0x1000u
296 #define IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT 12
297 #define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u
298 #define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13
299 #define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK 0x4000u
300 #define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_SHIFT 14
301 #define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_MASK 0x8000u
302 #define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_SHIFT 15
303 #define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_MASK 0x10000u
304 #define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_SHIFT 16
305 #define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK 0x20000u
306 #define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_SHIFT 17
307 #define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK 0x40000u
308 #define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_SHIFT 18
309 #define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_MASK 0x400000u
310 #define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_SHIFT 22
311 #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK 0x800000u
312 #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT 23
313 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK 0x30000000u
314 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT 28
315 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT))&IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK)
316 #define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK 0x40000000u
317 #define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_SHIFT 30
318 /* GPR2 Bit Fields */
319 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_MASK 0x1u
320 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_SHIFT 0
321 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_MASK 0x2u
322 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_SHIFT 1
323 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_MASK 0x4u
324 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_SHIFT 2
325 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_MASK 0x8u
326 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_SHIFT 3
327 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_MASK 0x10u
328 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_SHIFT 4
329 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_MASK 0x20u
330 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_SHIFT 5
331 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_MASK 0x40u
332 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_SHIFT 6
333 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_MASK 0x80u
334 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_SHIFT 7
335 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_MASK 0x100u
336 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_SHIFT 8
337 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_MASK 0x200u
338 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_SHIFT 9
339 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_MASK 0x400u
340 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_SHIFT 10
341 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_MASK 0x800u
342 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_SHIFT 11
343 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_MASK 0x1000u
344 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_SHIFT 12
345 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_MASK 0x2000u
346 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_SHIFT 13
347 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_MASK 0x4000u
348 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_SHIFT 14
349 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_MASK 0x8000u
350 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_SHIFT 15
351 #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK 0xFF0000u
352 #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT 16
353 #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT))&IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK)
354 #define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_MASK 0x1000000u
355 #define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_SHIFT 24
356 #define IOMUXC_GPR_GPR2_GPR_MQS_EN_MASK 0x2000000u
357 #define IOMUXC_GPR_GPR2_GPR_MQS_EN_SHIFT 25
358 #define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_MASK 0x4000000u
359 #define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_SHIFT 26
360 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_MASK 0x8000000u
361 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_SHIFT 27
362 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_MASK 0x10000000u
363 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_SHIFT 28
364 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_MASK 0x20000000u
365 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_SHIFT 29
366 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_MASK 0x40000000u
367 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_SHIFT 30
368 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_MASK 0x80000000u
369 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_SHIFT 31
370 /* GPR3 Bit Fields */
371 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_MASK 0x1u
372 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_SHIFT 0
373 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_MASK 0x2u
374 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_SHIFT 1
375 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_MASK 0x4u
376 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_SHIFT 2
377 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_MASK 0x8u
378 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_SHIFT 3
379 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_MASK 0x10u
380 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_SHIFT 4
381 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_MASK 0x20u
382 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_SHIFT 5
383 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_MASK 0x40u
384 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_SHIFT 6
385 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_MASK 0x80u
386 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_SHIFT 7
387 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_MASK 0x100u
388 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_SHIFT 8
389 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_MASK 0x200u
390 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_SHIFT 9
391 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_MASK 0x400u
392 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_SHIFT 10
393 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_MASK 0x800u
394 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_SHIFT 11
395 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_MASK 0x1000u
396 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_SHIFT 12
397 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_MASK 0x2000u
398 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_SHIFT 13
399 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_MASK 0x4000u
400 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_SHIFT 14
401 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_MASK 0x8000u
402 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_SHIFT 15
403 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_MASK 0x10000u
404 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_SHIFT 16
405 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_MASK 0x20000u
406 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_SHIFT 17
407 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_MASK 0x40000u
408 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_SHIFT 18
409 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_MASK 0x80000u
410 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_SHIFT 19
411 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_MASK 0x100000u
412 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_SHIFT 20
413 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_MASK 0x200000u
414 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_SHIFT 21
415 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_MASK 0x400000u
416 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_SHIFT 22
417 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_MASK 0x800000u
418 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_SHIFT 23
419 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_MASK 0x1000000u
420 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_SHIFT 24
421 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_MASK 0x2000000u
422 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_SHIFT 25
423 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_MASK 0x4000000u
424 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_SHIFT 26
425 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_MASK 0x8000000u
426 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_SHIFT 27
427 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_MASK 0x10000000u
428 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_SHIFT 28
429 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_MASK 0x20000000u
430 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_SHIFT 29
431 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_MASK 0x40000000u
432 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_SHIFT 30
433 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_MASK 0x80000000u
434 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_SHIFT 31
435 /* GPR4 Bit Fields */
436 #define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_MASK 0x1u
437 #define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_SHIFT 0
438 #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK 0x2u
439 #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_SHIFT 1
440 #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK 0x4u
441 #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_SHIFT 2
442 #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK 0x8u
443 #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT 3
444 #define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_MASK 0x10u
445 #define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_SHIFT 4
446 #define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_MASK 0x20u
447 #define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_SHIFT 5
448 #define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_MASK 0x40u
449 #define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_SHIFT 6
450 #define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_MASK 0x80u
451 #define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_SHIFT 7
452 #define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_MASK 0x10000u
453 #define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_SHIFT 16
454 #define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_MASK 0x20000u
455 #define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_SHIFT 17
456 #define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_MASK 0x40000u
457 #define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_SHIFT 18
458 #define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_MASK 0x80000u
459 #define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_SHIFT 19
460 #define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_MASK 0x100000u
461 #define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_SHIFT 20
462 #define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_MASK 0x200000u
463 #define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_SHIFT 21
464 #define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_MASK 0x400000u
465 #define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_SHIFT 22
466 #define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_MASK 0x800000u
467 #define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_SHIFT 23
468 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK 0x6000000u
469 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT 25
470 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK)
471 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK 0x18000000u
472 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT 27
473 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK)
474 /* GPR5 Bit Fields */
475 #define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_MASK 0x10u
476 #define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_SHIFT 4
477 #define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_MASK 0x20u
478 #define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_SHIFT 5
479 #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK 0x40u
480 #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT 6
481 #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK 0x80u
482 #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT 7
483 #define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_MASK 0x1000u
484 #define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_SHIFT 12
485 #define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_MASK 0x80000u
486 #define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_SHIFT 19
487 #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK 0x100000u
488 #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT 20
489 #define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_MASK 0x200000u
490 #define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_SHIFT 21
491 #define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_MASK 0x400000u
492 #define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_SHIFT 22
493 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_MASK 0x1000000u
494 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_SHIFT 24
495 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_MASK 0x2000000u
496 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_SHIFT 25
497 #define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_MASK 0x4000000u
498 #define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_SHIFT 26
499 #define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_MASK 0x8000000u
500 #define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_SHIFT 27
501 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_MASK 0x10000000u
502 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_SHIFT 28
503 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_MASK 0x20000000u
504 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_SHIFT 29
505 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_MASK 0x40000000u
506 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_SHIFT 30
507 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_MASK 0x80000000u
508 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_SHIFT 31
509 /* GPR6 Bit Fields */
510 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_MASK 0x1u
511 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_SHIFT 0
512 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_MASK 0x2u
513 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_SHIFT 1
514 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_MASK 0x4u
515 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_SHIFT 2
516 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_MASK 0x8u
517 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_SHIFT 3
518 /* GPR7 Bit Fields */
519 #define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_MASK 0x1u
520 #define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_SHIFT 0
521 #define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_MASK 0x2u
522 #define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_SHIFT 1
523 #define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_MASK 0x4u
524 #define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_SHIFT 2
525 #define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_MASK 0x8u
526 #define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_SHIFT 3
527 #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK 0x30u
528 #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT 4
529 #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK)
530 #define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_MASK 0x40u
531 #define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_SHIFT 6
532 #define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_MASK 0x80u
533 #define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_SHIFT 7
534 #define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_MASK 0x100u
535 #define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_SHIFT 8
536 #define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_MASK 0x200u
537 #define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_SHIFT 9
538 #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK 0xC00u
539 #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT 10
540 #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK)
541 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_MASK 0x1000u
542 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_SHIFT 12
543 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_MASK 0x2000u
544 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_SHIFT 13
545 /* GPR8 Bit Fields */
546 #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK 0xF8u
547 #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT 3
548 #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT))&IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK)
549 #define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK 0x100u
550 #define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_SHIFT 8
551 /* GPR9 Bit Fields */
552 #define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_MASK 0x1u
553 #define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_SHIFT 0
554 #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK 0x3Eu
555 #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT 1
556 #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT))&IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK)
557 /* GPR10 Bit Fields */
558 #define IOMUXC_GPR_GPR10_GPR0_BF0_MASK 0x1u
559 #define IOMUXC_GPR_GPR10_GPR0_BF0_SHIFT 0
560 #define IOMUXC_GPR_GPR10_GPR_DBG_EN_MASK 0x2u
561 #define IOMUXC_GPR_GPR10_GPR_DBG_EN_SHIFT 1
562 #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK 0x4u
563 #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT 2
564 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_MASK 0x8u
565 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_SHIFT 3
566 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK 0x3F0u
567 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT 4
568 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK)
569 /* GPR11 Bit Fields */
570 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK 0x1u
571 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT 0
572 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK 0x3Eu
573 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT 1
574 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK)
575 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_MASK 0x40u
576 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_SHIFT 6
577 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK 0x380u
578 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT 7
579 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK)
580 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK 0x400u
581 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT 10
582 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK 0x3800u
583 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT 11
584 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK)
585 /* GPR12 Bit Fields */
586 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_MASK 0x1u
587 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_SHIFT 0
588 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_MASK 0x2u
589 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_SHIFT 1
590 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_MASK 0x8u
591 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_SHIFT 3
592 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_MASK 0x10u
593 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_SHIFT 4
594 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_MASK 0x20u
595 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_SHIFT 5
596 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK 0xF000u
597 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT 12
598 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK)
599 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u
600 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT 17
601 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK)
602 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK 0xE00000u
603 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT 21
604 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK)
605 /* GPR13 Bit Fields */
606 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK 0x1u
607 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT 0
608 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK 0x2u
609 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT 1
610 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_MASK 0x4u
611 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_SHIFT 2
612 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_MASK 0x8u
613 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_SHIFT 3
614 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK 0x10u
615 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_SHIFT 4
616 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK 0x20u
617 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_SHIFT 5
618 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_MASK 0x40u
619 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_SHIFT 6
620 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_MASK 0x80u
621 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_SHIFT 7
622 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_MASK 0x100u
623 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_SHIFT 8
624 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_MASK 0x200u
625 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_SHIFT 9
626 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK 0x400u
627 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_SHIFT 10
628 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK 0x800u
629 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_SHIFT 11
630 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_MASK 0x1000u
631 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_SHIFT 12
632 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_MASK 0x2000u
633 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_SHIFT 13
634 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_MASK 0x4000u
635 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_SHIFT 14
636 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_MASK 0x8000u
637 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_SHIFT 15
638 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK 0xFF0000u
639 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT 16
640 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK)
641 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK 0xF000000u
642 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT 24
643 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK)
644 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_MASK 0x10000000u
645 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_SHIFT 28
646 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_MASK 0x20000000u
647 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_SHIFT 29
648 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_MASK 0x40000000u
649 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_SHIFT 30
650 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_MASK 0x80000000u
651 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_SHIFT 31
652 /* GPR14 Bit Fields */
653 #define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_MASK 0x1u
654 #define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_SHIFT 0
655 #define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_MASK 0x2u
656 #define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_SHIFT 1
657 /* GPR15 Bit Fields */
658 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_MASK 0x1u
659 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_SHIFT 0
660 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_MASK 0x2u
661 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_SHIFT 1
662 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK 0x3FFCu
663 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT 2
664 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK)
665 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK 0x3F0000u
666 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT 16
667 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK)
668 /* GPR16 Bit Fields */
669 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK 0x3u
670 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT 0
671 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK)
672 #define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_MASK 0x4u
673 #define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_SHIFT 2
674 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_MASK 0x8u
675 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_SHIFT 3
676 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_MASK 0x10u
677 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_SHIFT 4
678 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_MASK 0x20u
679 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_SHIFT 5
680 #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK 0x3C0u
681 #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT 6
682 #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK)
683 #define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_MASK 0x400u
684 #define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_SHIFT 10
685 #define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_MASK 0x800u
686 #define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_SHIFT 11
687 #define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_MASK 0x1000u
688 #define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_SHIFT 12
689 #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK 0xE000u
690 #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT 13
691 #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK)
692 #define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_MASK 0x10000u
693 #define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_SHIFT 16
694 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_MASK 0x20000u
695 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_SHIFT 17
696 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK 0x180000u
697 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT 19
698 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK)
699 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_MASK 0x200000u
700 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_SHIFT 21
701 #define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_MASK 0x400000u
702 #define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_SHIFT 22
703 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_MASK 0x800000u
704 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_SHIFT 23
705 /* GPR17 Bit Fields */
706 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK 0xFFu
707 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT 0
708 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK)
709 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK 0xFF00u
710 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT 8
711 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK)
712 /* GPR18 Bit Fields */
713 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK 0x7u
714 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT 0
715 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK)
716 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK 0x18u
717 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT 3
718 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK)
719 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK 0x60u
720 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT 5
721 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK)
722 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK 0x3F00u
723 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT 8
724 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK)
725 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_MASK 0x4000u
726 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_SHIFT 14
727 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK 0x7F0000u
728 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT 16
729 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK)
730 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK 0x3000000u
731 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT 24
732 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK)
733 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_MASK 0x4000000u
734 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_SHIFT 26
735 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_MASK 0x8000000u
736 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_SHIFT 27
737 #define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_MASK 0x10000000u
738 #define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_SHIFT 28
739 #define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_MASK 0x20000000u
740 #define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_SHIFT 29
741 /* GPR19 Bit Fields */
742 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_MASK 0x1u
743 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_SHIFT 0
744 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK 0xFF00u
745 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT 8
746 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT))&IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK)
747 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_MASK 0x10000u
748 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_SHIFT 16
749 #define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_MASK 0x20000u
750 #define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_SHIFT 17
751 /* GPR20 Bit Fields */
752 #define IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK 0x3Fu
753 #define IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT 0
754 #define IOMUXC_GPR_GPR20_GPR_LVDS_P(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK)
755 #define IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK 0x3F00u
756 #define IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT 8
757 #define IOMUXC_GPR_GPR20_GPR_LVDS_M(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK)
758 #define IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK 0x30000u
759 #define IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT 16
760 #define IOMUXC_GPR_GPR20_GPR_LVDS_S(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK)
761 #define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_MASK 0x1000000u
762 #define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_SHIFT 24
763 #define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_MASK 0x2000000u
764 #define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_SHIFT 25
765 #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK 0x38000000u
766 #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT 27
767 #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK)
768 /* GPR21 Bit Fields */
769 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK 0x7u
770 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT 0
771 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK)
772 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK 0x38u
773 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT 3
774 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK)
775 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK 0x1C0u
776 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT 6
777 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK)
778 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK 0xE00u
779 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT 9
780 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK)
781 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK 0x7000u
782 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT 12
783 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK)
784 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK 0x38000u
785 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT 15
786 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK)
787 #define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_MASK 0x40000u
788 #define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_SHIFT 18
789 #define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_MASK 0x80000u
790 #define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_SHIFT 19
791 /* GPR22 Bit Fields */
792 #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK 0xFF0000u
793 #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT 16
794 #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT))&IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK)
795 #define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_MASK 0x1000000u
796 #define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_SHIFT 24
797 #define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_MASK 0x2000000u
798 #define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_SHIFT 25
799 #define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_MASK 0x4000000u
800 #define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_SHIFT 26
801 #define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_MASK 0x8000000u
802 #define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_SHIFT 27
803 #define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_MASK 0x10000000u
804 #define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_SHIFT 28
805 #define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_MASK 0x20000000u
806 #define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_SHIFT 29
807 #define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_MASK 0x80000000u
808 #define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_SHIFT 31
810 #define IMX7D_GPR5_CSI1_MUX_CTRL_MASK (0x1 << 4)
811 #define IMX7D_GPR5_CSI1_MUX_CTRL_PARALLEL_CSI (0x0 << 4)
812 #define IMX7D_GPR5_CSI1_MUX_CTRL_MIPI_CSI (0x1 << 4)
816 /* mux and pad registers */
819 struct iomuxc_gpr_base_regs {
820 u32 gpr[23]; /* 0x000 */
823 /* ECSPI registers */
836 * CSPI register definitions
839 #define MXC_CSPICTRL_EN (1 << 0)
840 #define MXC_CSPICTRL_MODE (1 << 1)
841 #define MXC_CSPICTRL_XCH (1 << 2)
842 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
843 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
844 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
845 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
846 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
847 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
848 #define MXC_CSPICTRL_MAXBITS 0xfff
849 #define MXC_CSPICTRL_TC (1 << 7)
850 #define MXC_CSPICTRL_RXOVF (1 << 6)
851 #define MXC_CSPIPERIOD_32KHZ (1 << 15)
852 #define MAX_SPI_BYTES 32
854 /* Bit position inside CTRL register to be associated with SS */
855 #define MXC_CSPICTRL_CHAN 18
857 /* Bit position inside CON register to be associated with SS */
858 #define MXC_CSPICON_PHA 0 /* SCLK phase control */
859 #define MXC_CSPICON_POL 4 /* SCLK polarity */
860 #define MXC_CSPICON_SSPOL 12 /* SS polarity */
861 #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
863 #define MXC_SPI_BASE_ADDRESSES \
907 struct fuse_bank { /* offset 0x400 */
912 struct fuse_bank0_regs {
923 struct fuse_bank1_regs {
934 struct fuse_bank2_regs {
945 struct fuse_bank3_regs {
956 struct fuse_bank8_regs {
967 struct fuse_bank9_regs {
988 u16 wcr; /* Control */
989 u16 wsr; /* Service */
990 u16 wrsr; /* Reset Status */
991 u16 wicr; /* Interrupt Control */
992 u16 wmcr; /* Miscellaneous Control */
995 struct dbg_monitor_regs {
996 u32 ctrl[4]; /* Control */
997 u32 master_en[4]; /* Master enable */
998 u32 irq[4]; /* IRQ */
999 u32 trap_addr_low[4]; /* Trap address low */
1000 u32 trap_addr_high[4]; /* Trap address high */
1001 u32 trap_id[4]; /* Trap ID */
1002 u32 snvs_addr[4]; /* SNVS address */
1003 u32 snvs_data[4]; /* SNVS data */
1004 u32 snvs_info[4]; /* SNVS info */
1005 u32 version[4]; /* Version */
1009 u32 vir; /* Version information */
1011 u32 stat; /* Status */
1012 u32 intctrl; /* Interrupt and Control */
1013 u32 intstat; /* Interrupt Status */
1015 u32 mda[27]; /* Master Domain Assignment */
1017 u32 pdap[118]; /* Peripheral Domain Access Permissions */
1020 u32 mrsa; /* Memory Region Start Address */
1021 u32 mrea; /* Memory Region End Address */
1022 u32 mrc; /* Memory Region Control */
1023 u32 mrvs; /* Memory Region Violation Status */
1027 struct rdc_sema_regs {
1028 u8 gate[64]; /* Gate */
1029 u16 rstgt; /* Reset Gate */
1032 /* eLCDIF controller registers */
1033 struct mxs_lcdif_regs {
1034 u32 hw_lcdif_ctrl; /* 0x00 */
1035 u32 hw_lcdif_ctrl_set;
1036 u32 hw_lcdif_ctrl_clr;
1037 u32 hw_lcdif_ctrl_tog;
1038 u32 hw_lcdif_ctrl1; /* 0x10 */
1039 u32 hw_lcdif_ctrl1_set;
1040 u32 hw_lcdif_ctrl1_clr;
1041 u32 hw_lcdif_ctrl1_tog;
1042 u32 hw_lcdif_ctrl2; /* 0x20 */
1043 u32 hw_lcdif_ctrl2_set;
1044 u32 hw_lcdif_ctrl2_clr;
1045 u32 hw_lcdif_ctrl2_tog;
1046 u32 hw_lcdif_transfer_count; /* 0x30 */
1048 u32 hw_lcdif_cur_buf; /* 0x40 */
1050 u32 hw_lcdif_next_buf; /* 0x50 */
1052 u32 hw_lcdif_timing; /* 0x60 */
1054 u32 hw_lcdif_vdctrl0; /* 0x70 */
1055 u32 hw_lcdif_vdctrl0_set;
1056 u32 hw_lcdif_vdctrl0_clr;
1057 u32 hw_lcdif_vdctrl0_tog;
1058 u32 hw_lcdif_vdctrl1; /* 0x80 */
1060 u32 hw_lcdif_vdctrl2; /* 0x90 */
1062 u32 hw_lcdif_vdctrl3; /* 0xa0 */
1064 u32 hw_lcdif_vdctrl4; /* 0xb0 */
1066 u32 hw_lcdif_dvictrl0; /* 0xc0 */
1068 u32 hw_lcdif_dvictrl1; /* 0xd0 */
1070 u32 hw_lcdif_dvictrl2; /* 0xe0 */
1072 u32 hw_lcdif_dvictrl3; /* 0xf0 */
1074 u32 hw_lcdif_dvictrl4; /* 0x100 */
1076 u32 hw_lcdif_csc_coeffctrl0; /* 0x110 */
1078 u32 hw_lcdif_csc_coeffctrl1; /* 0x120 */
1080 u32 hw_lcdif_csc_coeffctrl2; /* 0x130 */
1082 u32 hw_lcdif_csc_coeffctrl3; /* 0x140 */
1084 u32 hw_lcdif_csc_coeffctrl4; /* 0x150 */
1086 u32 hw_lcdif_csc_offset; /* 0x160 */
1088 u32 hw_lcdif_csc_limit; /* 0x170 */
1090 u32 hw_lcdif_data; /* 0x180 */
1092 u32 hw_lcdif_bm_error_stat; /* 0x190 */
1094 u32 hw_lcdif_crc_stat; /* 0x1a0 */
1096 u32 hw_lcdif_lcdif_stat; /* 0x1b0 */
1098 u32 hw_lcdif_version; /* 0x1c0 */
1100 u32 hw_lcdif_debug0; /* 0x1d0 */
1102 u32 hw_lcdif_debug1; /* 0x1e0 */
1104 u32 hw_lcdif_debug2; /* 0x1f0 */
1106 u32 hw_lcdif_thres; /* 0x200 */
1108 u32 hw_lcdif_as_ctrl; /* 0x210 */
1110 u32 hw_lcdif_as_buf; /* 0x220 */
1112 u32 hw_lcdif_as_next_buf; /* 0x230 */
1114 u32 hw_lcdif_as_clrkeylow; /* 0x240 */
1116 u32 hw_lcdif_as_clrkeyhigh; /* 0x250 */
1118 u32 hw_lcdif_as_sync_delay; /* 0x260 */
1120 u32 hw_lcdif_as_debug3; /* 0x270 */
1122 u32 hw_lcdif_as_debug4; /* 0x280 */
1124 u32 hw_lcdif_as_debug5; /* 0x290 */
1127 #define MXS_LCDIF_BASE ELCDIF1_IPS_BASE_ADDR
1129 #define LCDIF_CTRL_SFTRST (1 << 31)
1130 #define LCDIF_CTRL_CLKGATE (1 << 30)
1131 #define LCDIF_CTRL_YCBCR422_INPUT (1 << 29)
1132 #define LCDIF_CTRL_READ_WRITEB (1 << 28)
1133 #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27)
1134 #define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26)
1135 #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21)
1136 #define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21
1137 #define LCDIF_CTRL_DVI_MODE (1 << 20)
1138 #define LCDIF_CTRL_BYPASS_COUNT (1 << 19)
1139 #define LCDIF_CTRL_VSYNC_MODE (1 << 18)
1140 #define LCDIF_CTRL_DOTCLK_MODE (1 << 17)
1141 #define LCDIF_CTRL_DATA_SELECT (1 << 16)
1142 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14)
1143 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14
1144 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12)
1145 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12
1146 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10)
1147 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10
1148 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10)
1149 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10)
1150 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10)
1151 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10)
1152 #define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8)
1153 #define LCDIF_CTRL_WORD_LENGTH_OFFSET 8
1154 #define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8)
1155 #define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8)
1156 #define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8)
1157 #define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8)
1158 #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7)
1159 #define LCDIF_CTRL_LCDIF_MASTER (1 << 5)
1160 #define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3)
1161 #define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2)
1162 #define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1)
1163 #define LCDIF_CTRL_RUN (1 << 0)
1165 #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27)
1166 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26)
1167 #define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25)
1168 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24)
1169 #define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23)
1170 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22)
1171 #define LCDIF_CTRL1_FIFO_CLEAR (1 << 21)
1172 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20)
1173 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16)
1174 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16
1175 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15)
1176 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14)
1177 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13)
1178 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12)
1179 #define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11)
1180 #define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10)
1181 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9)
1182 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8)
1183 #define LCDIF_CTRL1_BUSY_ENABLE (1 << 2)
1184 #define LCDIF_CTRL1_MODE86 (1 << 1)
1185 #define LCDIF_CTRL1_RESET (1 << 0)
1187 #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21)
1188 #define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21
1189 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21)
1190 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21)
1191 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21)
1192 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21)
1193 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21)
1194 #define LCDIF_CTRL2_BURST_LEN_8 (1 << 20)
1195 #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16)
1196 #define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16
1197 #define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16)
1198 #define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16)
1199 #define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16)
1200 #define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16)
1201 #define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16)
1202 #define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16)
1203 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12)
1204 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12
1205 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12)
1206 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12)
1207 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12)
1208 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12)
1209 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12)
1210 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12)
1211 #define LCDIF_CTRL2_READ_PACK_DIR (1 << 10)
1212 #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9)
1213 #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8)
1214 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4)
1215 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4
1216 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1)
1217 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1
1219 #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16)
1220 #define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16
1221 #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0)
1222 #define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0
1224 #define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff
1225 #define LCDIF_CUR_BUF_ADDR_OFFSET 0
1227 #define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff
1228 #define LCDIF_NEXT_BUF_ADDR_OFFSET 0
1230 #define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24)
1231 #define LCDIF_TIMING_CMD_HOLD_OFFSET 24
1232 #define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16)
1233 #define LCDIF_TIMING_CMD_SETUP_OFFSET 16
1234 #define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8)
1235 #define LCDIF_TIMING_DATA_HOLD_OFFSET 8
1236 #define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0)
1237 #define LCDIF_TIMING_DATA_SETUP_OFFSET 0
1239 #define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29)
1240 #define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28)
1241 #define LCDIF_VDCTRL0_VSYNC_POL (1 << 27)
1242 #define LCDIF_VDCTRL0_HSYNC_POL (1 << 26)
1243 #define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25)
1244 #define LCDIF_VDCTRL0_ENABLE_POL (1 << 24)
1245 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21)
1246 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20)
1247 #define LCDIF_VDCTRL0_HALF_LINE (1 << 19)
1248 #define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18)
1249 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff
1250 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0
1252 #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff
1253 #define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
1255 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
1256 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18
1257 #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff
1258 #define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0
1260 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29)
1261 #define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28)
1262 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16)
1263 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16
1264 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0)
1265 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0
1267 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29)
1268 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29
1269 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18)
1270 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff
1271 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0
1274 extern void check_cpu_temperature(void);
1276 extern void pcie_power_up(void);
1277 extern void pcie_power_off(void);
1279 /* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB
1280 * If boot from the other mode, USB0_PWD will keep reset value
1282 #define is_boot_from_usb(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \
1283 readl(USBOTG2_IPS_BASE_ADDR + 0x158))
1284 #define disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140)
1286 /* Boot device type */
1287 #define BOOT_TYPE_SD 0x1
1288 #define BOOT_TYPE_MMC 0x2
1289 #define BOOT_TYPE_NAND 0x3
1290 #define BOOT_TYPE_QSPI 0x4
1291 #define BOOT_TYPE_WEIM 0x5
1292 #define BOOT_TYPE_SPINOR 0x6
1294 struct bootrom_sw_info {
1296 u8 boot_dev_instance;
1306 #endif /* __ASSEMBLER__*/
1307 #endif /* __ASM_ARCH_MX7_IMX_REGS_H__ */