2 * (C) Copyright 2015 Google, Inc
4 * (C) Copyright 2008-2014 Rockchip Electronics
5 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
7 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef _ASM_ARCH_CRU_RK3288_H
10 #define _ASM_ARCH_CRU_RK3288_H
12 #define OSC_HZ (24 * 1000 * 1000)
14 #define APLL_HZ (1800 * 1000000)
15 #define GPLL_HZ (594 * 1000000)
16 #define CPLL_HZ (384 * 1000000)
17 #define NPLL_HZ (384 * 1000000)
19 /* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */
20 #define PD_BUS_ACLK_HZ 297000000
21 #define PD_BUS_HCLK_HZ 148500000
22 #define PD_BUS_PCLK_HZ 74250000
24 #define PERI_ACLK_HZ 148500000
25 #define PERI_HCLK_HZ 148500000
26 #define PERI_PCLK_HZ 74250000
37 u32 cru_clksel_con[43];
39 u32 cru_clkgate_con[19];
41 u32 cru_glb_srst_fst_value;
42 u32 cru_glb_srst_snd_value;
43 u32 cru_softrst_con[12];
55 check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
57 /* CRU_CLKSEL11_CON */
59 HSICPHY_DIV_SHIFT = 8,
60 HSICPHY_DIV_MASK = 0x3f,
64 MMC0_PLL_SELECT_CODEC = 0,
65 MMC0_PLL_SELECT_GENERAL,
66 MMC0_PLL_SELECT_24MHZ,
72 /* CRU_CLKSEL12_CON */
76 EMMC_PLL_SELECT_CODEC = 0,
77 EMMC_PLL_SELECT_GENERAL,
78 EMMC_PLL_SELECT_24MHZ,
85 SDIO0_PLL_SELECT_CODEC = 0,
86 SDIO0_PLL_SELECT_GENERAL,
87 SDIO0_PLL_SELECT_24MHZ,
90 SDIO0_DIV_MASK = 0x3f,
93 /* CRU_CLKSEL25_CON */
97 SPI1_PLL_SELECT_CODEC = 0,
98 SPI1_PLL_SELECT_GENERAL,
101 SPI1_DIV_MASK = 0x7f,
105 SPI0_PLL_SELECT_CODEC = 0,
106 SPI0_PLL_SELECT_GENERAL,
109 SPI0_DIV_MASK = 0x7f,
112 /* CRU_CLKSEL39_CON */
114 ACLK_HEVC_PLL_SHIFT = 0xe,
115 ACLK_HEVC_PLL_MASK = 3,
116 ACLK_HEVC_PLL_SELECT_CODEC = 0,
117 ACLK_HEVC_PLL_SELECT_GENERAL,
118 ACLK_HEVC_PLL_SELECT_NEW,
120 ACLK_HEVC_DIV_SHIFT = 8,
121 ACLK_HEVC_DIV_MASK = 0x1f,
125 SPI2_PLL_SELECT_CODEC = 0,
126 SPI2_PLL_SELECT_GENERAL,
129 SPI2_DIV_MASK = 0x7f,
134 NPLL_MODE_SHIFT = 0xe,
140 GPLL_MODE_SHIFT = 0xc,