1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
10 struct stv0991_cgu_regs {
11 u32 cpu_freq; /* offset 0x0 */
12 u32 icn2_freq; /* offset 0x4 */
13 u32 dma_freq; /* offset 0x8 */
14 u32 isp_freq; /* offset 0xc */
15 u32 h264_freq; /* offset 0x10 */
16 u32 osif_freq; /* offset 0x14 */
17 u32 ren_freq; /* offset 0x18 */
18 u32 tim_freq; /* offset 0x1c */
19 u32 sai_freq; /* offset 0x20 */
20 u32 eth_freq; /* offset 0x24 */
21 u32 i2c_freq; /* offset 0x28 */
22 u32 spi_freq; /* offset 0x2c */
23 u32 uart_freq; /* offset 0x30 */
24 u32 qspi_freq; /* offset 0x34 */
25 u32 sdio_freq; /* offset 0x38 */
26 u32 usi_freq; /* offset 0x3c */
27 u32 can_line_freq; /* offset 0x40 */
28 u32 debug_freq; /* offset 0x44 */
29 u32 trace_freq; /* offset 0x48 */
30 u32 stm_freq; /* offset 0x4c */
31 u32 eth_ctrl; /* offset 0x50 */
32 u32 reserved[3]; /* offset 0x54 */
33 u32 osc_ctrl; /* offset 0x60 */
34 u32 pll1_ctrl; /* offset 0x64 */
35 u32 pll1_freq; /* offset 0x68 */
36 u32 pll1_fract; /* offset 0x6c */
37 u32 pll1_spread; /* offset 0x70 */
38 u32 pll1_status; /* offset 0x74 */
39 u32 pll2_ctrl; /* offset 0x78 */
40 u32 pll2_freq; /* offset 0x7c */
41 u32 pll2_fract; /* offset 0x80 */
42 u32 pll2_spread; /* offset 0x84 */
43 u32 pll2_status; /* offset 0x88 */
44 u32 cgu_enable_1; /* offset 0x8c */
45 u32 cgu_enable_2; /* offset 0x90 */
46 u32 cgu_isp_pulse; /* offset 0x94 */
47 u32 cgu_h264_pulse; /* offset 0x98 */
48 u32 cgu_osif_pulse; /* offset 0x9c */
49 u32 cgu_ren_pulse; /* offset 0xa0 */
55 #define CLK_TMR_MCLK 1
56 #define CLK_TMR_PLL1 2
57 #define CLK_TMR_PLL2 3
58 #define MDIV_SHIFT_TMR 3
59 #define DIV_SHIFT_TMR 6
61 #define TIMER1_CLK_CFG (0 << DIV_SHIFT_TMR \
62 | 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK)
64 /* Clock Enable/Disable */
66 #define TIMER1_CLK_EN (1 << 15)
69 #define CLK_UART_MCLK 0
70 #define CLK_UART_PLL1 1
71 #define CLK_UART_PLL2 2
73 #define MDIV_SHIFT_UART 3
74 #define DIV_SHIFT_UART 6
76 #define UART_CLK_CFG (4 << DIV_SHIFT_UART \
77 | 1 << MDIV_SHIFT_UART | CLK_UART_MCLK)
79 /* CGU Ethernet clock config */
80 #define CLK_ETH_MCLK 0
81 #define CLK_ETH_PLL1 1
82 #define CLK_ETH_PLL2 2
84 #define MDIV_SHIFT_ETH 3
85 #define DIV_SHIFT_ETH 6
88 #define DIV_ETH_P2P 15
90 #define ETH_CLK_CFG (4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \
92 | 0 << DIV_SHIFT_ETH \
93 | 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1)
94 /* CGU Ethernet control */
96 #define ETH_CLK_TX_EXT_PHY 0
97 #define ETH_CLK_TX_125M 1
98 #define ETH_CLK_TX_25M 2
99 #define ETH_CLK_TX_2M5 3
100 #define ETH_CLK_TX_DIS 7
102 #define ETH_CLK_RX_EXT_PHY 0
103 #define ETH_CLK_RX_25M 1
104 #define ETH_CLK_RX_2M5 2
105 #define ETH_CLK_RX_DIS 3
106 #define RX_CLK_SHIFT 3
107 #define ETH_CLK_MASK ~(0x1F)
109 #define ETH_PHY_MODE_GMII 0
110 #define ETH_PHY_MODE_RMII 1
111 #define ETH_PHY_CLK_DIS 1
113 #define ETH_CLK_CTRL (ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \
114 | ETH_CLK_TX_EXT_PHY)
116 #define DIV_HCLK1_SHIFT 9
117 #define DIV_CRYP_SHIFT 6
118 #define MDIV_QSPI_SHIFT 3
120 #define CLK_QSPI_OSC 0
121 #define CLK_QSPI_MCLK 1
122 #define CLK_QSPI_PLL1 2
123 #define CLK_QSPI_PLL2 3
125 #define QSPI_CLK_CTRL (3 << DIV_HCLK1_SHIFT \
126 | 1 << DIV_CRYP_SHIFT \
127 | 0 << MDIV_QSPI_SHIFT \