2 * (C) Copyright 2010-2014
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _TEGRA_CLK_RST_H_
9 #define _TEGRA_CLK_RST_H_
11 /* PLL registers - there are several PLLs in the clock controller */
13 uint pll_base; /* the control register */
14 /* pll_out[0] is output A control, pll_out[1] is output B control */
16 uint pll_misc; /* other misc things */
19 /* PLL registers - there are several PLLs in the clock controller */
20 struct clk_pll_simple {
21 uint pll_base; /* the control register */
22 uint pll_misc; /* other misc things */
26 uint pllm_base; /* the control register */
27 uint pllm_out; /* output control */
28 uint pllm_misc1; /* misc1 */
29 uint pllm_misc2; /* misc2 */
32 /* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */
39 * Most PLLs use the clk_pll structure, but some have a simpler two-member
40 * structure for which we use clk_pll_simple. The reason for this non-
41 * othogonal setup is not stated.
44 TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */
45 TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */
46 TEGRA_CLK_REGS = 3, /* Number of clock enable regs L/H/U */
47 TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */
48 TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */
49 TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */
50 TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */
51 TEGRA_CLK_SOURCES_Y = 18, /* Number of ppl clock sources Y */
54 /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
56 uint crc_rst_src; /* _RST_SOURCE_0,0x00 */
57 uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */
58 uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */
59 uint crc_reserved0; /* reserved_0, 0x1C */
60 uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */
61 uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */
62 uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */
63 uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */
64 uint crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */
65 uint crc_prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */
66 uint crc_aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38 */
67 uint crc_reserved1; /* reserved_1, 0x3C */
68 uint crc_cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */
69 uint crc_clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */
70 uint crc_misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */
71 uint crc_clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */
72 uint crc_osc_ctrl; /* _OSC_CTRL_0, 0x50 */
73 uint crc_pll_lfsr; /* _PLL_LFSR_0, 0x54 */
74 uint crc_osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */
75 uint crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */
76 uint crc_reserved2[8]; /* reserved_2[8], 0x60-7C */
78 struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */
80 /* PLLs from 0xe0 to 0xf4 */
81 struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS];
83 uint crc_reserved10; /* _reserved_10, 0xF8 */
84 uint crc_reserved11; /* _reserved_11, 0xFC */
86 uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */
88 uint crc_reserved20[32]; /* _reserved_20, 0x200-27c */
90 uint crc_clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */
91 uint crc_clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */
92 uint crc_clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */
94 uint crc_rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */
95 uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */
96 uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */
98 uint crc_clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */
99 uint crc_clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */
100 uint crc_clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */
102 uint crc_rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */
103 uint crc_rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */
104 uint crc_rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */
106 uint crc_reserved21[17]; /* _reserved_21, 0x2b0-2f0 */
108 uint crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */
110 uint crc_reserved22[2]; /* _reserved_22, 0x2f8-2fc */
112 /* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */
113 struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS];
115 uint crc_reserved30[2]; /* _reserved_30, 0x318, 0x31c */
117 /* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */
118 struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS];
120 uint crc_reserved31[2]; /* _reserved_31, 0x338, 0x33c */
122 uint crc_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */
123 uint crc_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */
125 /* Additional (T30) registers */
126 uint crc_clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */
127 uint crc_clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */
129 uint crc_reserved32[2]; /* _reserved_32, 0x350,0x354 */
131 uint crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */
132 uint crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */
133 uint crc_cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */
134 uint crc_super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */
135 uint crc_cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */
136 uint crc_super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
137 uint crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */
138 uint crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */
139 uint crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */
140 uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */
141 uint crc_cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */
142 uint crc_reserved33[9]; /* _reserved_33, 0x38c-3ac */
143 uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* 0x3B0-0x42C */
144 /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
145 struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
146 /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
147 struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
148 /* Additional (T114+) registers */
149 uint crc_rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */
150 uint crc_rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */
151 uint crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */
152 uint crc_rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45C */
153 uint crc_clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */
154 uint crc_clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */
155 uint crc_clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */
156 uint crc_clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46C */
157 uint crc_cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */
158 uint crc_reserved40[1]; /* _reserved_40, 0x474 */
159 uint crc_intstatus; /* __INTSTATUS_0, 0x478 */
160 uint crc_intmask; /* __INTMASK_0, 0x47C */
161 uint crc_utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */
162 uint crc_utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */
163 uint crc_utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */
165 uint crc_plle_aux; /* _PLLE_AUX_0, 0x48C */
166 uint crc_sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */
167 uint crc_sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */
168 uint crc_pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */
170 uint crc_prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49C */
171 uint crc_audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */
172 uint crc_audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */
173 uint crc_audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */
174 uint crc_audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */
175 uint crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
176 uint crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
178 uint crc_plld2_base; /* _PLLD2_BASE_0, 0x4B8 */
179 uint crc_plld2_misc; /* _PLLD2_MISC_0, 0x4BC */
180 uint crc_utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */
181 uint crc_pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */
182 uint crc_pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */
183 uint crs_reserved_50[7]; /* _reserved_50, 0x4CC-0x4E4 */
184 uint crc_pllc2_base; /* _PLLC2_BASE_0, 0x4E8 */
185 uint crc_pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4EC */
186 uint crc_pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4F0 */
187 uint crc_pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4F4 */
188 uint crc_pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4F8 */
189 uint crc_pllc3_base; /* _PLLC3_BASE_0, 0x4FC */
190 uint crc_pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */
191 uint crc_pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */
192 uint crc_pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */
193 uint crc_pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50C */
194 uint crc_pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */
195 uint crc_pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */
196 uint crc_pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */
197 uint crc_xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51C */
198 uint crc_xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */
199 uint crc_plle_aux1; /* _PLLE_AUX1_0, 0x524 */
200 uint crc_pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */
201 uint crc_utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */
202 uint crc_pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */
203 uint crc_xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */
204 uint crc_reserved51[1]; /* _reserved_51, 0x538 */
205 uint crc_clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53C */
206 uint crc_clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */
207 uint crc_clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */
208 uint crc_pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */
209 uint crc_pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54C */
210 uint crc_pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */
211 uint crc_reserved52[1]; /* _reserved_52, 0x554 */
212 uint crc_super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
213 uint crc_spare_reg0; /* _SPARE_REG0_0, 0x55C */
214 u32 _rsv32[4]; /* 0x560-0x56c */
215 u32 crc_plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */
216 u32 _rsv32_1[7]; /* 0x574-58c */
217 struct clk_pll_simple plldp; /* _PLLDP_BASE, 0x590 _PLLDP_MISC */
218 u32 crc_plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
220 /* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */
221 uint _rsrv32_2[25]; /* _0x59C - 0x5FC */
222 uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */
224 /* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */
225 uint crc_reserved61[5]; /* _reserved_61, 0x680 - 0x690 */
227 * NOTE: PLLA1 regs are in the middle of this Y region. Break this in
228 * two later if PLLA1 is needed, but for now this is cleaner.
230 uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */
233 /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
234 #define CPU3_CLK_STP_SHIFT 11
235 #define CPU2_CLK_STP_SHIFT 10
236 #define CPU1_CLK_STP_SHIFT 9
237 #define CPU0_CLK_STP_SHIFT 8
238 #define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT)
240 /* CLK_RST_CONTROLLER_PLLx_BASE_0 */
241 #define PLL_BYPASS_SHIFT 31
242 #define PLL_BYPASS_MASK (1U << PLL_BYPASS_SHIFT)
244 #define PLL_ENABLE_SHIFT 30
245 #define PLL_ENABLE_MASK (1U << PLL_ENABLE_SHIFT)
247 #define PLL_BASE_OVRRIDE_MASK (1U << 28)
249 #define PLL_LOCK_SHIFT 27
250 #define PLL_LOCK_MASK (1U << PLL_LOCK_SHIFT)
252 #define PLL_DIVP_SHIFT 20
253 #define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT)
254 /* Special case for T210 PLLU DIVP */
255 #define PLLU_DIVP_SHIFT 16
257 #define PLL_DIVN_SHIFT 8
258 #define PLL_DIVN_MASK (0x3ffU << PLL_DIVN_SHIFT)
260 #define PLL_DIVM_SHIFT 0
261 #define PLL_DIVM_MASK (0x1f << PLL_DIVM_SHIFT)
263 /* CLK_RST_CONTROLLER_PLLx_OUTx_0 */
264 #define PLL_OUT_RSTN (1 << 0)
265 #define PLL_OUT_CLKEN (1 << 1)
266 #define PLL_OUT_OVRRIDE (1 << 2)
268 #define PLL_OUT_RATIO_SHIFT 8
269 #define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT)
271 /* CLK_RST_CONTROLLER_PLLx_MISC_0 */
272 #define PLL_DCCON_SHIFT 20
273 #define PLL_DCCON_MASK (1U << PLL_DCCON_SHIFT)
275 #define PLL_LOCK_ENABLE_SHIFT 18
276 #define PLL_LOCK_ENABLE_MASK (1U << PLL_LOCK_ENABLE_SHIFT)
278 #define PLL_CPCON_SHIFT 8
279 #define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT)
281 #define PLL_LFCON_SHIFT 4
282 #define PLL_LFCON_MASK (15U << PLL_LFCON_SHIFT)
284 /* CPCON/LFCON replaced by KCP/KVCO in T210 PLLU */
285 #define PLLU_KVCO_SHIFT 24
286 #define PLLU_KVCO_MASK (3U << PLLU_KVCO_SHIFT)
287 #define PLLU_KCP_SHIFT 25
288 #define PLLU_KCP_MASK (1U << PLLU_KCP_SHIFT)
290 #define PLLU_VCO_FREQ_SHIFT 20
291 #define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT)
293 #define PLLP_OUT1_OVR (1 << 2)
294 #define PLLP_OUT2_OVR (1 << 18)
295 #define PLLP_OUT3_OVR (1 << 2)
296 #define PLLP_OUT4_OVR (1 << 18)
297 #define PLLP_OUT1_RATIO 8
298 #define PLLP_OUT2_RATIO 24
299 #define PLLP_OUT3_RATIO 8
300 #define PLLP_OUT4_RATIO 24
303 IN_408_OUT_204_DIVISOR = 2,
304 IN_408_OUT_102_DIVISOR = 6,
305 IN_408_OUT_48_DIVISOR = 15,
306 IN_408_OUT_9_6_DIVISOR = 83,
309 #define PLLP_OUT1_RSTN_DIS (1 << 0)
310 #define PLLP_OUT1_RSTN_EN (0 << 0)
311 #define PLLP_OUT1_CLKEN (1 << 1)
312 #define PLLP_OUT2_RSTN_DIS (1 << 16)
313 #define PLLP_OUT2_RSTN_EN (0 << 16)
314 #define PLLP_OUT2_CLKEN (1 << 17)
316 #define PLLP_OUT3_RSTN_DIS (1 << 0)
317 #define PLLP_OUT3_RSTN_EN (0 << 0)
318 #define PLLP_OUT3_CLKEN (1 << 1)
319 #define PLLP_OUT4_RSTN_DIS (1 << 16)
320 #define PLLP_OUT4_RSTN_EN (0 << 16)
321 #define PLLP_OUT4_CLKEN (1 << 17)
323 /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */
324 #define PLLU_POWERDOWN (1 << 16)
325 #define PLL_ENABLE_POWERDOWN (1 << 14)
326 #define PLL_ACTIVE_POWERDOWN (1 << 12)
328 /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */
329 #define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
330 #define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
331 #define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
333 /* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */
334 #define OSC_XOE_SHIFT 0
335 #define OSC_XOE_MASK (1 << OSC_XOE_SHIFT)
336 #define OSC_XOE_ENABLE (1 << OSC_XOE_SHIFT)
337 #define OSC_XOBP_SHIFT 1
338 #define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT)
339 #define OSC_XOFS_SHIFT 4
340 #define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT)
341 #define OSC_DRIVE_STRENGTH 7
344 * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits
345 * but can be 16. We could use knowledge we have to restrict the mask in
346 * the 8-bit cases (the divider_bits value returned by
347 * get_periph_clock_source()) but it does not seem worth it since the code
348 * already checks the ranges of values it is writing, in clk_get_divider().
350 #define OUT_CLK_DIVISOR_SHIFT 0
351 #define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT)
353 #define OUT_CLK_SOURCE_31_30_SHIFT 30
354 #define OUT_CLK_SOURCE_31_30_MASK (3U << OUT_CLK_SOURCE_31_30_SHIFT)
356 #define OUT_CLK_SOURCE_31_29_SHIFT 29
357 #define OUT_CLK_SOURCE_31_29_MASK (7U << OUT_CLK_SOURCE_31_29_SHIFT)
359 /* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */
360 #define OUT_CLK_SOURCE_31_28_SHIFT 28
361 #define OUT_CLK_SOURCE_31_28_MASK (15U << OUT_CLK_SOURCE_31_28_SHIFT)
363 /* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
364 #define SCLK_SYS_STATE_SHIFT 28U
365 #define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT)
367 SCLK_SYS_STATE_STDBY,
370 SCLK_SYS_STATE_IRQ = 4U,
371 SCLK_SYS_STATE_FIQ = 8U,
373 #define SCLK_COP_FIQ_MASK (1 << 27)
374 #define SCLK_CPU_FIQ_MASK (1 << 26)
375 #define SCLK_COP_IRQ_MASK (1 << 25)
376 #define SCLK_CPU_IRQ_MASK (1 << 24)
378 #define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT 12
379 #define SCLK_SWAKEUP_FIQ_SOURCE_MASK \
380 (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
381 #define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT 8
382 #define SCLK_SWAKEUP_IRQ_SOURCE_MASK \
383 (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
384 #define SCLK_SWAKEUP_RUN_SOURCE_SHIFT 4
385 #define SCLK_SWAKEUP_RUN_SOURCE_MASK \
386 (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
387 #define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT 0
389 #define SCLK_SWAKEUP_IDLE_SOURCE_MASK \
390 (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
393 SCLK_SOURCE_PLLC_OUT1,
394 SCLK_SOURCE_PLLP_OUT4,
395 SCLK_SOURCE_PLLP_OUT3,
396 SCLK_SOURCE_PLLP_OUT2,
399 SCLK_SOURCE_PLLM_OUT1,
401 #define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12)
402 #define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8)
403 #define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4)
404 #define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0)
406 /* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER */
407 #define SUPER_SCLK_ENB_SHIFT 31U
408 #define SUPER_SCLK_ENB_MASK (1U << 31)
409 #define SUPER_SCLK_DIVIDEND_SHIFT 8
410 #define SUPER_SCLK_DIVIDEND_MASK (0xff << SUPER_SCLK_DIVIDEND_SHIFT)
411 #define SUPER_SCLK_DIVISOR_SHIFT 0
412 #define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT)
414 /* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */
415 #define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7
416 #define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT)
417 #define CLK_SYS_RATE_AHB_RATE_SHIFT 4
418 #define CLK_SYS_RATE_AHB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
419 #define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3
420 #define CLK_SYS_RATE_PCLK_DISABLE_MASK (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT)
421 #define CLK_SYS_RATE_APB_RATE_SHIFT 0
422 #define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
424 /* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */
425 #define CLR_CPURESET0 (1 << 0)
426 #define CLR_CPURESET1 (1 << 1)
427 #define CLR_CPURESET2 (1 << 2)
428 #define CLR_CPURESET3 (1 << 3)
429 #define CLR_DBGRESET0 (1 << 12)
430 #define CLR_DBGRESET1 (1 << 13)
431 #define CLR_DBGRESET2 (1 << 14)
432 #define CLR_DBGRESET3 (1 << 15)
433 #define CLR_CORERESET0 (1 << 16)
434 #define CLR_CORERESET1 (1 << 17)
435 #define CLR_CORERESET2 (1 << 18)
436 #define CLR_CORERESET3 (1 << 19)
437 #define CLR_CXRESET0 (1 << 20)
438 #define CLR_CXRESET1 (1 << 21)
439 #define CLR_CXRESET2 (1 << 22)
440 #define CLR_CXRESET3 (1 << 23)
441 #define CLR_L2RESET (1 << 24)
442 #define CLR_NONCPURESET (1 << 29)
443 #define CLR_PRESETDBG (1 << 30)
445 /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */
446 #define CLR_CPU0_CLK_STP (1 << 8)
447 #define CLR_CPU1_CLK_STP (1 << 9)
448 #define CLR_CPU2_CLK_STP (1 << 10)
449 #define CLR_CPU3_CLK_STP (1 << 11)
451 /* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */
452 #define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29)
454 /* CRC_CLK_ENB_V_SET_0 0x440 */
455 #define SET_CLK_ENB_CPUG_ENABLE (1 << 0)
456 #define SET_CLK_ENB_CPULP_ENABLE (1 << 1)
457 #define SET_CLK_ENB_MSELECT_ENABLE (1 << 3)
459 /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */
460 #define PLL_ACTIVE_POWERDOWN (1 << 12)
461 #define PLL_ENABLE_POWERDOWN (1 << 14)
462 #define PLLU_POWERDOWN (1 << 16)
464 /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */
465 #define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
466 #define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
467 #define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
469 /* CLK_RST_CONTROLLER_PLLX_MISC_3 */
470 #define PLLX_IDDQ_SHIFT 3
471 #define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT)
473 /* CLK_RST_PLLDP_SS_CFG */
474 #define PLLDP_SS_CFG_CLAMP (1 << 22)
475 #define PLLDP_SS_CFG_UNDOCUMENTED (1 << 24)
476 #define PLLDP_SS_CFG_DITHER (1 << 28)
478 #endif /* _TEGRA_CLK_RST_H_ */