2 * Copyright (c) 2011 The Chromium OS Authors.
4 * SPDX-License-Identifier: GPL-2.0+
7 /* Tegra clock control functions */
9 #ifndef _TEGRA_CLOCK_H_
10 #define _TEGRA_CLOCK_H_
12 /* Set of oscillator frequencies supported in the internal API. */
14 /* All in MHz, so 13_0 is 13.0MHz */
24 MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */
29 #include <asm/arch/clock-tables.h>
30 /* PLL stabilization delay in usec */
31 #define CLOCK_PLL_STABLE_DELAY_US 300
33 /* return the current oscillator clock frequency */
34 enum clock_osc_freq clock_get_osc_freq(void);
37 * Start PLL using the provided configuration parameters.
40 * @param divm input divider
41 * @param divn feedback divider
42 * @param divp post divider 2^n
43 * @param cpcon charge pump setup control
44 * @param lfcon loop filter setup control
46 * @returns monotonic time in us that the PLL will be stable
48 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
49 u32 divp, u32 cpcon, u32 lfcon);
52 * Set PLL output frequency
54 * @param clkid clock id
55 * @param pllout pll output id
56 * @param rate desired output rate
58 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
60 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout,
64 * Read low-level parameters of a PLL.
66 * @param id clock id to read (note: USB is not supported)
67 * @param divm returns input divider
68 * @param divn returns feedback divider
69 * @param divp returns post divider 2^n
70 * @param cpcon returns charge pump setup control
71 * @param lfcon returns loop filter setup control
73 * @returns 0 if ok, -1 on error (invalid clock id)
75 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
76 u32 *divp, u32 *cpcon, u32 *lfcon);
83 void clock_enable(enum periph_id clkid);
90 void clock_disable(enum periph_id clkid);
93 * Set whether a clock is enabled or disabled.
96 * @param enable 1 to enable, 0 to disable
98 void clock_set_enable(enum periph_id clkid, int enable);
101 * Reset a peripheral. This puts it in reset, waits for a delay, then takes
102 * it out of reset and waits for th delay again.
104 * @param periph_id peripheral to reset
105 * @param us_delay time to delay in microseconds
107 void reset_periph(enum periph_id periph_id, int us_delay);
110 * Put a peripheral into or out of reset.
112 * @param periph_id peripheral to reset
113 * @param enable 1 to put into reset, 0 to take out of reset
115 void reset_set_enable(enum periph_id periph_id, int enable);
118 /* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
120 /* Things we can hold in reset for each CPU */
122 crc_rst_de = 1 << 4, /* What is de? */
123 crc_rst_watchdog = 1 << 8,
124 crc_rst_debug = 1 << 12,
128 * Put parts of the CPU complex into or out of reset.\
130 * @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3)
131 * @param which which parts of the complex to affect (OR of crc_reset_id)
132 * @param reset 1 to assert reset, 0 to de-assert
134 void reset_cmplx_set_enable(int cpu, int which, int reset);
137 * Set the source for a peripheral clock. This plus the divisor sets the
138 * clock rate. You need to look up the datasheet to see the meaning of the
139 * source parameter as it changes for each peripheral.
141 * Warning: This function is only for use pre-relocation. Please use
142 * clock_start_periph_pll() instead.
144 * @param periph_id peripheral to adjust
145 * @param source source clock (0, 1, 2 or 3)
147 void clock_ll_set_source(enum periph_id periph_id, unsigned source);
150 * Set the source and divisor for a peripheral clock. This sets the
151 * clock rate. You need to look up the datasheet to see the meaning of the
152 * source parameter as it changes for each peripheral.
154 * Warning: This function is only for use pre-relocation. Please use
155 * clock_start_periph_pll() instead.
157 * @param periph_id peripheral to adjust
158 * @param source source clock (0, 1, 2 or 3)
159 * @param divisor divisor value to use
161 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
165 * Start a peripheral PLL clock at the given rate. This also resets the
168 * @param periph_id peripheral to start
169 * @param parent PLL id of required parent clock
170 * @param rate Required clock rate in Hz
171 * @return rate selected in Hz, or -1U if something went wrong
173 unsigned clock_start_periph_pll(enum periph_id periph_id,
174 enum clock_id parent, unsigned rate);
177 * Returns the rate of a peripheral clock in Hz. Since the caller almost
178 * certainly knows the parent clock (having just set it) we require that
179 * this be passed in so we don't need to work it out.
181 * @param periph_id peripheral to start
182 * @param parent PLL id of parent clock (used to calculate rate, you
184 * @return clock rate of peripheral in Hz
186 unsigned long clock_get_periph_rate(enum periph_id periph_id,
187 enum clock_id parent);
190 * Adjust peripheral PLL clock to the given rate. This does not reset the
191 * peripheral. If a second stage divisor is not available, pass NULL for
192 * extra_div. If it is available, then this parameter will return the
193 * divisor selected (which will be a power of 2 from 1 to 256).
195 * @param periph_id peripheral to start
196 * @param parent PLL id of required parent clock
197 * @param rate Required clock rate in Hz
198 * @param extra_div value for the second-stage divisor (NULL if one is
200 * @return rate selected in Hz, or -1U if something went wrong
202 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
203 enum clock_id parent, unsigned rate, int *extra_div);
206 * Returns the clock rate of a specified clock, in Hz.
208 * @param parent PLL id of clock to check
209 * @return rate of clock in Hz
211 unsigned clock_get_rate(enum clock_id clkid);
214 * Start up a UART using low-level calls
216 * Prior to relocation clock_start_periph_pll() cannot be called. This
217 * function provides a way to set up a UART using low-level calls which
218 * do not require BSS.
220 * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1)
222 void clock_ll_start_uart(enum periph_id periph_id);
225 * Decode a peripheral ID from a device tree node.
227 * This works by looking up the peripheral's 'clocks' node and reading out
228 * the second cell, which is the clock number / peripheral ID.
230 * @param blob FDT blob to use
231 * @param node Node to look at
232 * @return peripheral ID, or PERIPH_ID_NONE if none
234 enum periph_id clock_decode_periph_id(const void *blob, int node);
237 * Checks if the oscillator bypass is enabled (XOBP bit)
239 * @return 1 if bypass is enabled, 0 if not
241 int clock_get_osc_bypass(void);
244 * Checks that clocks are valid and prints a warning if not
246 * @return 0 if ok, -1 on error
248 int clock_verify(void);
250 /* Initialize the clocks */
251 void clock_init(void);
253 /* Initialize the PLLs */
254 void clock_early_init(void);
256 /* Returns a pointer to the clock source register for a peripheral */
257 u32 *get_periph_source_reg(enum periph_id periph_id);
260 * Given a peripheral ID and the required source clock, this returns which
261 * value should be programmed into the source mux for that peripheral.
263 * There is special code here to handle the one source type with 5 sources.
265 * @param periph_id peripheral to start
266 * @param source PLL id of required parent clock
267 * @param mux_bits Set to number of bits in mux register: 2 or 4
268 * @param divider_bits Set to number of divider bits (8 or 16)
269 * @return mux value (0-4, or -1 if not found)
271 int get_periph_clock_source(enum periph_id periph_id,
272 enum clock_id parent, int *mux_bits, int *divider_bits);
275 * Convert a device tree clock ID to our peripheral ID. They are mostly
276 * the same but we are very cautious so we check that a valid clock ID is
279 * @param clk_id Clock ID according to tegra30 device tree binding
280 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
282 enum periph_id clk_id_to_periph_id(int clk_id);
285 * Set the output frequency you want for each PLL clock.
286 * PLL output frequencies are programmed by setting their N, M and P values.
287 * The governing equations are:
288 * VCO = (Fi / m) * n, Fo = VCO / (2^p)
289 * where Fo is the output frequency from the PLL.
290 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
291 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
292 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
294 * @param n PLL feedback divider(DIVN)
295 * @param m PLL input divider(DIVN)
296 * @param p post divider(DIVP)
297 * @param cpcon base PLL charge pump(CPCON)
298 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
299 * be overriden), 1 if PLL is already correct
301 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
303 /* return 1 if a peripheral ID is in range */
304 #define clock_type_id_isvalid(id) ((id) >= 0 && \
305 (id) < CLOCK_TYPE_COUNT)
307 /* return 1 if a periphc_internal_id is in range */
308 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
309 (id) < PERIPHC_COUNT)
311 /* SoC-specific TSC init */
312 void arch_timer_init(void);
314 #endif /* _TEGRA_CLOCK_H_ */