2 * Copyright (c) 2011 The Chromium OS Authors.
3 * See file CREDITS for list of people who contributed to this
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 /* USB Controller (USBx_CONTROLLER_) regs */
62 uint periodic_list_base;
69 uint reserved6; /* is this port_sc1 on some controllers? */
76 uint endpt_nak_enable;
87 uint endpt_setup_stat;
93 uint reserved11[0x80];
97 uint phy_vbus_sensors;
98 uint phy_vbus_wakeup_id;
99 uint phy_alt_vbus_sys;
102 uint usb1_legacy_ctrl;
106 uint ulpi_timing_ctrl_0;
107 uint ulpi_timing_ctrl_1;
111 uint reserved14[64 * 3];
116 uint utmip_xcvr_cfg0;
117 uint utmip_bias_cfg0;
120 uint utmip_hsrx_cfg0;
121 uint utmip_hsrx_cfg1;
122 uint utmip_fslsrx_cfg0;
123 uint utmip_fslsrx_cfg1;
127 uint utmip_misc_cfg0;
128 uint utmip_misc_cfg1;
129 uint utmip_debounce_cfg0;
132 uint utmip_bat_chrg_cfg0;
133 uint utmip_spare_cfg0;
134 uint utmip_xcvr_cfg1;
135 uint utmip_bias_cfg1;
139 /* USB1_LEGACY_CTRL */
140 #define USB1_NO_LEGACY_MODE 1
142 #define VBUS_SENSE_CTL_SHIFT 1
143 #define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT)
144 #define VBUS_SENSE_CTL_VBUS_WAKEUP 0
145 #define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1
146 #define VBUS_SENSE_CTL_AB_SESS_VLD 2
147 #define VBUS_SENSE_CTL_A_SESS_VLD 3
149 /* USB2_IF_ULPI_TIMING_CTRL_0 */
150 #define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
151 #define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
153 /* USB2_IF_ULPI_TIMING_CTRL_1 */
154 #define ULPI_DATA_TRIMMER_LOAD (1 << 0)
155 #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
156 #define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
157 #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
158 #define ULPI_DIR_TRIMMER_LOAD (1 << 24)
159 #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
161 /* USBx_IF_USB_SUSP_CTRL_0 */
162 #define ULPI_PHY_ENB (1 << 13)
163 #define UTMIP_PHY_ENB (1 << 12)
164 #define UTMIP_RESET (1 << 11)
165 #define USB_PHY_CLK_VALID (1 << 7)
166 #define USB_SUSP_CLR (1 << 5)
168 /* USBx_UTMIP_MISC_CFG1 */
169 #define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
170 #define UTMIP_PLLU_STABLE_COUNT_MASK \
171 (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
172 #define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18
173 #define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \
174 (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
175 #define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
177 /* USBx_UTMIP_PLL_CFG1_0 */
178 #define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27
179 #define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \
180 (0xf << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
181 #define UTMIP_XTAL_FREQ_COUNT_SHIFT 0
182 #define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff
184 /* USBx_UTMIP_BIAS_CFG1_0 */
185 #define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3
186 #define UTMIP_BIAS_PDTRK_COUNT_MASK \
187 (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
189 #define UTMIP_DEBOUNCE_CFG0_SHIFT 0
190 #define UTMIP_DEBOUNCE_CFG0_MASK 0xffff
192 /* USBx_UTMIP_TX_CFG0_0 */
193 #define UTMIP_FS_PREAMBLE_J (1 << 19)
195 /* USBx_UTMIP_BAT_CHRG_CFG0_0 */
196 #define UTMIP_PD_CHRG 1
198 /* USBx_UTMIP_XCVR_CFG0_0 */
199 #define UTMIP_XCVR_LSBIAS_SE (1 << 21)
201 /* USBx_UTMIP_SPARE_CFG0_0 */
202 #define FUSE_SETUP_SEL (1 << 3)
204 /* USBx_UTMIP_HSRX_CFG0_0 */
205 #define UTMIP_IDLE_WAIT_SHIFT 15
206 #define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT)
207 #define UTMIP_ELASTIC_LIMIT_SHIFT 10
208 #define UTMIP_ELASTIC_LIMIT_MASK \
209 (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
211 /* USBx_UTMIP_HSRX_CFG0_1 */
212 #define UTMIP_HS_SYNC_START_DLY_SHIFT 1
213 #define UTMIP_HS_SYNC_START_DLY_MASK \
214 (0xf << UTMIP_HS_SYNC_START_DLY_SHIFT)
216 /* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
217 #define IC_ENB1 (1 << 3)
219 /* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
221 #define PTS_MASK (3U << PTS_SHIFT)
223 #define PTS_RESERVED 1
225 #define PTS_ICUSB_SER 3
227 #define STS (1 << 29)
228 #define WKOC (1 << 22)
229 #define WKDS (1 << 21)
230 #define WKCN (1 << 20)
232 /* USBx_UTMIP_XCVR_CFG0_0 */
233 #define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
234 #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
235 #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
237 /* USBx_UTMIP_XCVR_CFG1_0 */
238 #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
239 #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
240 #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
242 /* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
243 #define VBUS_VLD_STS (1 << 26)
246 /* Setup USB on the board */
247 int board_usb_init(const void *blob);
249 #endif /* _TEGRA_USB_H_ */