3 * Texas Instruments, <www.ti.com>
4 * Aneesh V <aneesh@ti.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 /* Cortex-A9 revisions */
12 #define MIDR_CORTEX_A9_R0P1 0x410FC091
13 #define MIDR_CORTEX_A9_R1P2 0x411FC092
14 #define MIDR_CORTEX_A9_R1P3 0x411FC093
15 #define MIDR_CORTEX_A9_R2P10 0x412FC09A
17 /* Cortex-A15 revisions */
18 #define MIDR_CORTEX_A15_R0P0 0x410FC0F0
19 #define MIDR_CORTEX_A15_R2P2 0x412FC0F2
22 #define CCSIDR_LINE_SIZE_OFFSET 0
23 #define CCSIDR_LINE_SIZE_MASK 0x7
24 #define CCSIDR_ASSOCIATIVITY_OFFSET 3
25 #define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3)
26 #define CCSIDR_NUM_SETS_OFFSET 13
27 #define CCSIDR_NUM_SETS_MASK (0x7FFF << 13)
30 * Values for InD field in CSSELR
31 * Selects the type of cache
33 #define ARMV7_CSSELR_IND_DATA_UNIFIED 0
34 #define ARMV7_CSSELR_IND_INSTRUCTION 1
36 /* Values for Ctype fields in CLIDR */
37 #define ARMV7_CLIDR_CTYPE_NO_CACHE 0
38 #define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1
39 #define ARMV7_CLIDR_CTYPE_DATA_ONLY 2
40 #define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3
41 #define ARMV7_CLIDR_CTYPE_UNIFIED 4
44 #include <linux/types.h>
47 * CP15 Barrier instructions
48 * Please note that we have separate barrier instructions in ARMv7
49 * However, we use the CP15 based instructtions because we use
50 * -march=armv5 in U-Boot
52 #define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))
53 #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
54 #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
56 void v7_outer_cache_enable(void);
57 void v7_outer_cache_disable(void);
58 void v7_outer_cache_flush_all(void);
59 void v7_outer_cache_inval_all(void);
60 void v7_outer_cache_flush_range(u32 start, u32 end);
61 void v7_outer_cache_inval_range(u32 start, u32 end);
63 #endif /* ! __ASSEMBLY__ */