3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/system.h>
26 #include <asm/cache.h>
27 #include <linux/compiler.h>
29 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
31 DECLARE_GLOBAL_DATA_PTR;
33 void __arm_init_before_mmu(void)
36 void arm_init_before_mmu(void)
37 __attribute__((weak, alias("__arm_init_before_mmu")));
39 static void cp_delay (void)
43 /* copro seems to need some delay between reading and writing */
44 for (i = 0; i < 100; i++)
46 asm volatile("" : : : "memory");
49 void set_section_dcache(int section, enum dcache_option option)
51 u32 *page_table = (u32 *)gd->arch.tlb_addr;
54 value = (section << MMU_SECTION_SHIFT) | (3 << 10);
56 page_table[section] = value;
59 void __mmu_page_table_flush(unsigned long start, unsigned long stop)
61 debug("%s: Warning: not implemented\n", __func__);
64 void mmu_page_table_flush(unsigned long start, unsigned long stop)
65 __attribute__((weak, alias("__mmu_page_table_flush")));
67 void mmu_set_region_dcache_behaviour(u32 start, int size,
68 enum dcache_option option)
70 u32 *page_table = (u32 *)gd->arch.tlb_addr;
73 end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
74 start = start >> MMU_SECTION_SHIFT;
75 debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size,
77 for (upto = start; upto < end; upto++)
78 set_section_dcache(upto, option);
79 mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
82 __weak void dram_bank_mmu_setup(int bank)
87 debug("%s: bank: %d\n", __func__, bank);
88 for (i = bd->bi_dram[bank].start >> 20;
89 i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
91 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
92 set_section_dcache(i, DCACHE_WRITETHROUGH);
94 set_section_dcache(i, DCACHE_WRITEBACK);
99 /* to activate the MMU we need to set up virtual memory: use 1M areas */
100 static inline void mmu_setup(void)
105 arm_init_before_mmu();
106 /* Set up an identity-mapping for all 4GB, rw for everyone */
107 for (i = 0; i < 4096; i++)
108 set_section_dcache(i, DCACHE_OFF);
110 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
111 dram_bank_mmu_setup(i);
114 /* Copy the page table address to cp15 */
115 asm volatile("mcr p15, 0, %0, c2, c0, 0"
116 : : "r" (gd->arch.tlb_addr) : "memory");
117 /* Set the access control to all-supervisor */
118 asm volatile("mcr p15, 0, %0, c3, c0, 0"
120 /* and enable the mmu */
121 reg = get_cr(); /* get control reg. */
126 static int mmu_enabled(void)
128 return get_cr() & CR_M;
131 /* cache_bit must be either CR_I or CR_C */
132 static void cache_enable(uint32_t cache_bit)
136 /* The data cache is not active unless the mmu is enabled too */
137 if ((cache_bit == CR_C) && !mmu_enabled())
139 reg = get_cr(); /* get control reg. */
141 set_cr(reg | cache_bit);
144 /* cache_bit must be either CR_I or CR_C */
145 static void cache_disable(uint32_t cache_bit)
152 if (cache_bit == CR_C) {
153 /* if cache isn;t enabled no need to disable */
154 if ((reg & CR_C) != CR_C)
156 /* if disabling data cache, disable mmu too */
161 if (cache_bit == (CR_C | CR_M))
163 set_cr(reg & ~cache_bit);
167 #ifdef CONFIG_SYS_ICACHE_OFF
168 void icache_enable (void)
173 void icache_disable (void)
178 int icache_status (void)
180 return 0; /* always off */
183 void icache_enable(void)
188 void icache_disable(void)
193 int icache_status(void)
195 return (get_cr() & CR_I) != 0;
199 #ifdef CONFIG_SYS_DCACHE_OFF
200 void dcache_enable (void)
205 void dcache_disable (void)
210 int dcache_status (void)
212 return 0; /* always off */
215 void dcache_enable(void)
220 void dcache_disable(void)
225 int dcache_status(void)
227 return (get_cr() & CR_C) != 0;