2 * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
4 * Copyright (C) 2005 David Brownell
5 * Copyright (C) 2005 Ivan Kokshaysky
6 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/at91_pmc.h>
15 #include <asm/arch/clk.h>
17 #if !defined(CONFIG_AT91FAMILY)
18 # error You need to define CONFIG_AT91FAMILY in your board config!
21 #define EN_PLLB_TIMEOUT 500
23 DECLARE_GLOBAL_DATA_PTR;
25 static unsigned long at91_css_to_rate(unsigned long css)
28 case AT91_PMC_MCKR_CSS_SLOW:
29 return CONFIG_SYS_AT91_SLOW_CLOCK;
30 case AT91_PMC_MCKR_CSS_MAIN:
31 return gd->arch.main_clk_rate_hz;
32 case AT91_PMC_MCKR_CSS_PLLA:
33 return gd->arch.plla_rate_hz;
34 case AT91_PMC_MCKR_CSS_PLLB:
35 return gd->arch.pllb_rate_hz;
41 #ifdef CONFIG_USB_ATMEL
42 static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
44 unsigned i, div = 0, mul = 0, diff = 1 << 30;
45 unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
47 /* PLL output max 240 MHz (or 180 MHz per errata) */
48 if (out_freq > 240000000)
51 for (i = 1; i < 256; i++) {
56 * PLL input between 1MHz and 32MHz per spec, but lower
57 * frequences seem necessary in some cases so allow 100K.
58 * Warning: some newer products need 2MHz min.
60 input = main_freq / i;
61 #if defined(CONFIG_AT91SAM9G20)
70 mul1 = out_freq / input;
71 #if defined(CONFIG_AT91SAM9G20)
80 diff1 = out_freq - input * mul1;
91 if (i == 256 && diff > (out_freq >> 5))
93 return ret | ((mul - 1) << 16) | div;
99 static u32 at91_pll_rate(u32 freq, u32 reg)
104 mul = (reg >> 16) & 0x7ff;
114 int at91_clock_init(unsigned long main_clock)
117 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
118 #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
121 * When the bootloader initialized the main oscillator correctly,
122 * there's no problem using the cycle counter. But if it didn't,
123 * or when using oscillator bypass mode, we must be told the speed
128 tmp = readl(&pmc->mcfr);
129 } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
130 tmp &= AT91_PMC_MCFR_MAINF_MASK;
131 main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
134 gd->arch.main_clk_rate_hz = main_clock;
136 /* report if PLLA is more than mildly overclocked */
137 gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
139 #ifdef CONFIG_USB_ATMEL
141 * USB clock init: choose 48 MHz PLLB value,
142 * disable 48MHz clock during usb peripheral suspend.
144 * REVISIT: assumes MCK doesn't derive from PLLB!
146 gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
147 AT91_PMC_PLLBR_USBDIV_2;
148 gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
149 gd->arch.at91_pllb_usb_init);
153 * MCK and CPU derive from one of those primary clocks.
154 * For now, assume this parentage won't change.
156 mckr = readl(&pmc->mckr);
157 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
158 || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
159 /* plla divisor by 2 */
160 gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
162 gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
163 freq = gd->arch.mck_rate_hz;
165 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
166 #if defined(CONFIG_AT91SAM9G20)
167 /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
168 gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
169 freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
170 if (mckr & AT91_PMC_MCKR_MDIV_MASK)
171 freq /= 2; /* processor clock division */
172 #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
173 || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
180 gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
181 (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
183 : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
185 gd->arch.mck_rate_hz = freq /
186 (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
188 gd->arch.cpu_clk_rate_hz = freq;
193 #if !defined(AT91_PLL_LOCK_TIMEOUT)
194 #define AT91_PLL_LOCK_TIMEOUT 1000000
197 void at91_plla_init(u32 pllar)
199 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
201 writel(pllar, &pmc->pllar);
202 while (!(readl(&pmc->sr) & AT91_PMC_LOCKA))
205 void at91_pllb_init(u32 pllbr)
207 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
209 writel(pllbr, &pmc->pllbr);
210 while (!(readl(&pmc->sr) & AT91_PMC_LOCKB))
214 void at91_mck_init(u32 mckr)
216 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
219 tmp = readl(&pmc->mckr);
220 tmp &= ~AT91_PMC_MCKR_PRES_MASK;
221 tmp |= mckr & AT91_PMC_MCKR_PRES_MASK;
222 writel(tmp, &pmc->mckr);
223 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
226 tmp = readl(&pmc->mckr);
227 tmp &= ~AT91_PMC_MCKR_MDIV_MASK;
228 tmp |= mckr & AT91_PMC_MCKR_MDIV_MASK;
229 writel(tmp, &pmc->mckr);
230 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
233 tmp = readl(&pmc->mckr);
234 tmp &= ~AT91_PMC_MCKR_PLLADIV_MASK;
235 tmp |= mckr & AT91_PMC_MCKR_PLLADIV_MASK;
236 writel(tmp, &pmc->mckr);
237 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
240 tmp = readl(&pmc->mckr);
241 tmp &= ~AT91_PMC_MCKR_CSS_MASK;
242 tmp |= mckr & AT91_PMC_MCKR_CSS_MASK;
243 writel(tmp, &pmc->mckr);
244 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
248 int at91_pllb_clk_enable(u32 pllbr)
250 struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
251 ulong start_time, tmp_time;
253 start_time = get_timer(0);
254 writel(pllbr, &pmc->pllbr);
255 while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) {
256 tmp_time = get_timer(0);
257 if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
258 printf("ERROR: failed to enable PLLB\n");
266 int at91_pllb_clk_disable(void)
268 struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
269 ulong start_time, tmp_time;
271 start_time = get_timer(0);
272 writel(0, &pmc->pllbr);
273 while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) {
274 tmp_time = get_timer(0);
275 if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
276 printf("ERROR: failed to disable PLLB\n");