1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Memory Setup stuff - taken from blob memsetup.S
5 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
6 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
8 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
9 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/at91_pmc.h>
15 #include <asm/arch/at91_wdt.h>
16 #include <asm/arch/at91_pio.h>
17 #include <asm/arch/at91_matrix.h>
18 #include <asm/arch/at91sam9_sdramc.h>
19 #include <asm/arch/at91sam9_smc.h>
20 #include <asm/arch/at91_rstc.h>
21 #ifdef CONFIG_ATMEL_LEGACY
22 #include <asm/arch/at91sam9_matrix.h>
24 #ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
25 #define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
29 .type lowlevel_init,function
33 adr r5, POS1 /* r5 = POS1 run time */
34 ldr r0, =POS1 /* r0 = POS1 compile */
35 sub r5, r5, r0 /* r0 = CONFIG_SYS_TEXT_BASE-1 */
37 /* memory control configuration 1 */
51 /* ----------------------------------------------------------------------------
53 * ----------------------------------------------------------------------------
54 * - Check if the PLL is already initialized
55 * ----------------------------------------------------------------------------
57 ldr r1, =(AT91_ASM_PMC_MCKR)
63 /* ---------------------------------------------------------------------------
64 * - Enable the Main Oscillator
65 * ---------------------------------------------------------------------------
67 ldr r1, =(AT91_ASM_PMC_MOR)
68 ldr r2, =(AT91_ASM_PMC_SR)
69 /* Main oscillator Enable register PMC_MOR: */
70 ldr r0, =CONFIG_SYS_MOR_VAL
73 /* Reading the PMC Status to detect when the Main Oscillator is enabled */
74 mov r4, #AT91_PMC_IXR_MOSCS
78 cmp r3, #AT91_PMC_IXR_MOSCS
81 /* ----------------------------------------------------------------------------
83 * ----------------------------------------------------------------------------
85 * ----------------------------------------------------------------------------
87 ldr r1, =(AT91_ASM_PMC_PLLAR)
88 ldr r0, =CONFIG_SYS_PLLAR_VAL
91 /* Reading the PMC Status register to detect when the PLLA is locked */
92 mov r4, #AT91_PMC_IXR_LOCKA
96 cmp r3, #AT91_PMC_IXR_LOCKA
99 /* ----------------------------------------------------------------------------
101 * ----------------------------------------------------------------------------
102 * - Switch on the Main Oscillator
103 * ----------------------------------------------------------------------------
105 ldr r1, =(AT91_ASM_PMC_MCKR)
107 /* -Master Clock Controller register PMC_MCKR */
108 ldr r0, =CONFIG_SYS_MCKR1_VAL
111 /* Reading the PMC Status to detect when the Master clock is ready */
112 mov r4, #AT91_PMC_IXR_MCKRDY
116 cmp r3, #AT91_PMC_IXR_MCKRDY
119 ldr r0, =CONFIG_SYS_MCKR2_VAL
122 /* Reading the PMC Status to detect when the Master clock is ready */
123 mov r4, #AT91_PMC_IXR_MCKRDY
127 cmp r3, #AT91_PMC_IXR_MCKRDY
131 /* ----------------------------------------------------------------------------
132 * - memory control configuration 2
133 * ----------------------------------------------------------------------------
135 ldr r0, =(AT91_ASM_SDRAMC_TR)
154 /* everything is fine now */
160 .word AT91_ASM_WDT_MR
161 .word CONFIG_SYS_WDTC_WDMR_VAL
162 /* configure PIOx as EBI0 D[16-31] */
163 #if defined(CONFIG_AT91SAM9263)
164 .word AT91_ASM_PIOD_PDR
165 .word CONFIG_SYS_PIOD_PDR_VAL1
166 .word AT91_ASM_PIOD_PUDR
167 .word CONFIG_SYS_PIOD_PPUDR_VAL
168 .word AT91_ASM_PIOD_ASR
169 .word CONFIG_SYS_PIOD_PPUDR_VAL
170 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
171 || defined(CONFIG_AT91SAM9G20)
172 .word AT91_ASM_PIOC_PDR
173 .word CONFIG_SYS_PIOC_PDR_VAL1
174 .word AT91_ASM_PIOC_PUDR
175 .word CONFIG_SYS_PIOC_PPUDR_VAL
177 .word AT91_ASM_MATRIX_CSA0
178 .word CONFIG_SYS_MATRIX_EBICSA_VAL
181 .word AT91_ASM_SMC_MODE0
182 .word CONFIG_SYS_SMC0_MODE0_VAL
184 .word AT91_ASM_SMC_CYCLE0
185 .word CONFIG_SYS_SMC0_CYCLE0_VAL
187 .word AT91_ASM_SMC_PULSE0
188 .word CONFIG_SYS_SMC0_PULSE0_VAL
190 .word AT91_ASM_SMC_SETUP0
191 .word CONFIG_SYS_SMC0_SETUP0_VAL
194 .word AT91_ASM_SDRAMC_MR
195 .word CONFIG_SYS_SDRC_MR_VAL1
196 .word AT91_ASM_SDRAMC_TR
197 .word CONFIG_SYS_SDRC_TR_VAL1
198 .word AT91_ASM_SDRAMC_CR
199 .word CONFIG_SYS_SDRC_CR_VAL
200 .word AT91_ASM_SDRAMC_MDR
201 .word CONFIG_SYS_SDRC_MDR_VAL
202 .word AT91_ASM_SDRAMC_MR
203 .word CONFIG_SYS_SDRC_MR_VAL2
204 .word CONFIG_SYS_SDRAM_BASE
205 .word CONFIG_SYS_SDRAM_VAL1
206 .word AT91_ASM_SDRAMC_MR
207 .word CONFIG_SYS_SDRC_MR_VAL3
208 .word CONFIG_SYS_SDRAM_BASE
209 .word CONFIG_SYS_SDRAM_VAL2
210 .word CONFIG_SYS_SDRAM_BASE
211 .word CONFIG_SYS_SDRAM_VAL3
212 .word CONFIG_SYS_SDRAM_BASE
213 .word CONFIG_SYS_SDRAM_VAL4
214 .word CONFIG_SYS_SDRAM_BASE
215 .word CONFIG_SYS_SDRAM_VAL5
216 .word CONFIG_SYS_SDRAM_BASE
217 .word CONFIG_SYS_SDRAM_VAL6
218 .word CONFIG_SYS_SDRAM_BASE
219 .word CONFIG_SYS_SDRAM_VAL7
220 .word CONFIG_SYS_SDRAM_BASE
221 .word CONFIG_SYS_SDRAM_VAL8
222 .word CONFIG_SYS_SDRAM_BASE
223 .word CONFIG_SYS_SDRAM_VAL9
224 .word AT91_ASM_SDRAMC_MR
225 .word CONFIG_SYS_SDRC_MR_VAL4
226 .word CONFIG_SYS_SDRAM_BASE
227 .word CONFIG_SYS_SDRAM_VAL10
228 .word AT91_ASM_SDRAMC_MR
229 .word CONFIG_SYS_SDRC_MR_VAL5
230 .word CONFIG_SYS_SDRAM_BASE
231 .word CONFIG_SYS_SDRAM_VAL11
232 .word AT91_ASM_SDRAMC_TR
233 .word CONFIG_SYS_SDRC_TR_VAL2
234 .word CONFIG_SYS_SDRAM_BASE
235 .word CONFIG_SYS_SDRAM_VAL12
236 /* User reset enable*/
237 .word AT91_ASM_RSTC_MR
238 .word CONFIG_SYS_RSTC_RMR_VAL
239 #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
240 /* MATRIX_MCFG - REMAP all masters */
241 .word AT91_ASM_MATRIX_MCFG