2 * Copyright (C) 2012 Samsung Electronics
4 * Author: Donghwa Lee <dh09.lee@samsung.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #define msleep(a) udelay(a * 1000)
14 #define DP_TIMEOUT_LOOP_COUNT 100
18 #define EXYNOS_DP_SUCCESS 0
25 struct edp_disp_info {
29 unsigned int h_sync_width;
30 unsigned int h_back_porch;
31 unsigned int h_front_porch;
34 unsigned int v_sync_width;
35 unsigned int v_back_porch;
36 unsigned int v_front_porch;
38 unsigned int v_sync_rate;
41 struct edp_link_train_info {
42 unsigned int lt_status;
45 unsigned int cr_loop[4];
49 struct edp_video_info {
50 unsigned int master_mode;
51 unsigned int bist_mode;
52 unsigned int bist_pattern;
54 unsigned int h_sync_polarity;
55 unsigned int v_sync_polarity;
56 unsigned int interlaced;
58 unsigned int color_space;
59 unsigned int dynamic_range;
60 unsigned int ycbcr_coeff;
61 unsigned int color_depth;
64 struct exynos_dp_priv {
65 struct edp_disp_info disp_info;
66 struct edp_link_train_info lt_info;
67 struct edp_video_info video_info;
69 /*below info get from panel during training*/
70 unsigned char lane_bw;
71 unsigned char lane_cnt;
72 unsigned char dpcd_rev;
73 /*support enhanced frame cap */
74 unsigned char dpcd_efc;
75 struct exynos_dp *regs;
78 enum analog_power_block {
117 DP_LANE_BW_1_62 = 0x06,
118 DP_LANE_BW_2_70 = 0x0a,
128 DP_DPCD_REV_10 = 0x10,
129 DP_DPCD_REV_11 = 0x11,
142 PRE_EMPHASIS_LEVEL_0,
143 PRE_EMPHASIS_LEVEL_1,
144 PRE_EMPHASIS_LEVEL_2,
145 PRE_EMPHASIS_LEVEL_3,
171 WHITE_GRAY_BALCKBAR_32,
172 WHITE_GRAY_BALCKBAR_64,
183 VIDEO_TIMING_FROM_CAPTURE,
184 VIDEO_TIMING_FROM_REGISTER
188 struct exynos_dp_platform_data {
189 struct exynos_dp_priv *edp_dev_info;
192 #ifdef CONFIG_EXYNOS_DP
193 unsigned int exynos_init_dp(void);
195 unsigned int exynos_init_dp(void)
201 #endif /* _DP_INFO_H */